summaryrefslogtreecommitdiff
path: root/lib/Target/Mips/MipsSEISelLowering.cpp
Commit message (Collapse)AuthorAge
...
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-11
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-11
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ↵Daniel Sanders2013-10-11
| | | | | | from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-07
| | | | | | | | | | | | | | | | | accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not ↵Daniel Sanders2013-10-01
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-27
| | | | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-27
| | | | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-27
| | | | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Tidy upDaniel Sanders2013-09-27
| | | | | | | | | | | | | lowerMSABinaryIntr, lowerMSABinaryImmIntr, lowerMSABranchIntr, and lowerMSAUnaryIntr were trivially small functions. Inlined them into their callers. lowerMSASplat now takes its callers SDLoc instead of making a new one. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191503 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Expand all truncstores and loadexts for MSA as well as DSPDaniel Sanders2013-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added missing check in performSRACombineDaniel Sanders2013-09-27
| | | | | | | | | | Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D1755 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-24
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-24
| | | | | | IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Non-constant BUILD_VECTOR's should be expanded to ↵Daniel Sanders2013-09-24
| | | | | | | | | | INSERT_VECTOR_ELT instead of memory operations. The resulting code is the same length, but doesnt cause memory traffic or latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191297 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. ↵Daniel Sanders2013-09-24
| | | | | | | | | not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching andi, ori, nori, and xori from normal ↵Daniel Sanders2013-09-24
| | | | | | IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191293 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-24
| | | | | | (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-24
| | | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-24
| | | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching slli, srai, and srli from normal IR ↵Daniel Sanders2013-09-24
| | | | | | (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191285 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. ↵Daniel Sanders2013-09-23
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191203 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-23
| | | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191198 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191195 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. ↵Daniel Sanders2013-09-23
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191194 91177308-0d34-0410-b5e6-96231b3b80d8
* Partially revert r191192: Fix -Wunused-variable error when assertions are ↵Daniel Sanders2013-09-23
| | | | | | | | | | disabled and -Werror is in use. An unrelated change crept in because 'svn revert' isn't recursive by default. The unrelated changes have been reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191193 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix -Wunused-variable error when assertions are disabled and -Werror is in use.Daniel Sanders2013-09-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191192 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented build_vector using ldi, fill, and custom ↵Daniel Sanders2013-09-23
| | | | | | | | | | | | | | | | | | | SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv ↵Daniel Sanders2013-09-11
| | | | | | from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, ↵Daniel Sanders2013-09-11
| | | | | | fsqrt, and fsub from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching div_[su] from normal IR (i.e. not ↵Daniel Sanders2013-09-11
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-11
| | | | | | | | The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Separate the configuration of int/float vector types since they ↵Daniel Sanders2013-09-11
| | | | | | | | | | will diverge soon No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190506 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] When double precision loads and stores are split into two i32 loads andAkira Hatanaka2013-09-09
| | | | | | | | | | stores, make sure the load or store that accesses the higher half does not have an alignment that is larger than the offset from the original address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190318 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-07
| | | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-30
| | | | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-28
| | | | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Split MSA128 regset into size-specific sets containing the same ↵Daniel Sanders2013-08-23
| | | | | | registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189095 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add support for calling convention CC_MipsO32_FP64, which is used ↵Akira Hatanaka2013-08-20
| | | | | | | | | | | when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-15
| | | | | | | | | | | | | | Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename DSPRegs.Akira Hatanaka2013-08-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added initial MSA support.Jack Carter2013-08-13
| | | | | | | | | | | | | * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-27 16:27:36 +0000