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path: root/lib/Target/Mips/MipsSubtarget.cpp
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* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-29
| | | | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
* Undo a change made in r140254.Akira Hatanaka2011-09-21
| | | | | | | | | MipsArchVersion needs to be initialized to Mips32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140261 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsArchVersion does not need to be in the initialization list and MipsABIAkira Hatanaka2011-09-21
| | | | | | | | | should be initialized to UnknownABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140254 91177308-0d34-0410-b5e6-96231b3b80d8
* Set ABI if it hasn't been set on the command line.Akira Hatanaka2011-09-21
| | | | | | | | Check if architecture & ABI combination is valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140230 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-09
| | | | | | | | | | removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-24
| | | | | | | These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-14
| | | | | | | registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-11
| | | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-09
| | | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-08
| | | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-01
| | | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-30
| | | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka2011-04-15
| | | | | | in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka2011-04-15
| | | | | | change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes2011-03-04
| | | | | | Hatanaka, Akira git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
* reintroduce support for Mips "small" section handling. This is Chris Lattner2009-08-13
| | | | | | | | | implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78900 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore some "small section" support code, reverting my patch from r76936.Chris Lattner2009-08-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78894 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove -disable-mips-abicall and -enable-mips-absolute-call command-line Eli Friedman2009-08-03
| | | | | | | | | | | | | | | options, which don't appear to be useful. -enable-mips-absolute-call is completely unused (and unless I'm mistaken, is supposed to have the same effect that -relocation-model=dynamic-no-pic should have), and -disable-mips-abicall appears to be effectively a synonym for -relocation-model=static. Adjust the few users of hasABICall to checks which seem more appropriate. Update MipsSubtarget, MipsTargetMachine, and MipselTargetMachine to synchronize with recent changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77938 91177308-0d34-0410-b5e6-96231b3b80d8
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-02
| | | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
* remove more remnants of small section support.Chris Lattner2009-07-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76936 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes2009-05-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed Bug 2751Bruno Cardoso Lopes2008-09-15
| | | | | | | | | | | | | http://llvm.org/bugs/show_bug.cgi?id=2751 Abicall was enabled even when static code model was provided in the command line. The correct behavior is to disable abicall when static is specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56228 91177308-0d34-0410-b5e6-96231b3b80d8
* Make option variables static, so they won't cause nameclashAnton Korobeynikov2008-08-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55203 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT nodeBruno Cardoso Lopes2008-08-13
| | | | | | | | | | | | | | | | | is lowered properly and covers everything LowerSELECT_CC did. Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This avoid the ugly instruction by instruction checking in printOperand. Added a swap instruction present in the allegrex core. Added two conditional instructions present in the allegrex core : MOVZ and MOVN. They both allow a more efficient SELECT operation for integers. Also added SELECT patterns to optimize MOVZ and MOVN usage. The brcond and setcc patterns were cleaned: redundant and suboptimal patterns were removed. The suboptimals were replaced by more efficient ones. Fixed some instructions that were using immZExt16 instead of immSExt16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54724 91177308-0d34-0410-b5e6-96231b3b80d8
* Support added for ctlz intrinsic, test case added.Bruno Cardoso Lopes2008-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54516 91177308-0d34-0410-b5e6-96231b3b80d8
* Match raw "psp" triple target, as done by the homebrew toolchain.Bruno Cardoso Lopes2008-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54514 91177308-0d34-0410-b5e6-96231b3b80d8
* Added new features to represent specific instructions groupsBruno Cardoso Lopes2008-07-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54213 91177308-0d34-0410-b5e6-96231b3b80d8
* Added initial support for small sections on Mips.Bruno Cardoso Lopes2008-07-21
| | | | | | | | Added gp_rel relocations to support addressing small section contents. Added command line to specify small section threshold in bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53869 91177308-0d34-0410-b5e6-96231b3b80d8
* Added Subtarget support into RegisterInfoBruno Cardoso Lopes2008-07-14
| | | | | | | | | | | | | | Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and -mno-shared). HasAbsoluteCall is not implemented but HasABICall is the default for o32 ABI. Now, both should help into a more accurate relocation types implementation. Added IsLinux is needed to choose between asm directives. Instruction name strings cleanup. AsmPrinter improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53551 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed features usage.Bruno Cardoso Lopes2008-07-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53277 91177308-0d34-0410-b5e6-96231b3b80d8
* Several changes to Mips backend, experimental fp support being the mostBruno Cardoso Lopes2008-07-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
* Some Mips minor fixesBruno Cardoso Lopes2008-06-04
| | | | | | | | Added support for mips little endian arch => mipsel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51923 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Better processor definitionBruno Cardoso Lopes2007-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43749 91177308-0d34-0410-b5e6-96231b3b80d8
* support for Schedule included on Mips.tdBruno Cardoso Lopes2007-08-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41159 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial Mips support, here we go! =)Bruno Cardoso Lopes2007-06-06
- Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
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