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path: root/lib/Target/NVPTX/NVPTXISelLowering.h
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* [NVPTX] Implement fma and imad contraction as target DAGCombiner patternsJustin Holewinski2014-06-27
| | | | | | This also introduces DAGCombiner patterns for mul.wide to multiply two smaller integers and produce a larger integer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211935 91177308-0d34-0410-b5e6-96231b3b80d8
* Move NVPTX subtarget dependent variables from the target machineEric Christopher2014-06-27
| | | | | | to the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211860 91177308-0d34-0410-b5e6-96231b3b80d8
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-29
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. NVPTX edition git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207505 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add preliminary intrinsics and codegen support for textures/surfacesJustin Holewinski2014-04-09
| | | | | | This commit adds intrinsics and codegen support for the surface read/write and texture read instructions that take an explicit sampler parameter. Codegen operates on image handles at the PTX level, but falls back to direct replacement of handles with kernel arguments if image handles are not enabled. Note that image handles are explicitly disabled for all target architectures in this change (to be enabled later). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205907 91177308-0d34-0410-b5e6-96231b3b80d8
* Change shouldSplitVectorElementType to better match the description.Matt Arsenault2014-03-31
| | | | | | Pass the entire vector type, and not just the element. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205247 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix handling of indirect callsJustin Holewinski2013-11-15
| | | | | | Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194810 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] We dont use NVBuiltin anymoreJustin Holewinski2013-07-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185335 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Clean up comparison/select/convert patterns and factor out PTX ↵Justin Holewinski2013-06-28
| | | | | | | | instructions from their patterns Test case is no breakage git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185175 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is ↵Justin Holewinski2013-06-28
| | | | | | rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185174 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add infrastructure for vector loads/stores of parametersJustin Holewinski2013-06-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185171 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Default pointer type doesn't make sense for getParamSymbol()Justin Holewinski2013-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184831 91177308-0d34-0410-b5e6-96231b3b80d8
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-25
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Run clang-format on all NVPTX sources.Justin Holewinski2013-03-30
| | | | | | | Hopefully this resolves any outstanding style issues and gives us an automated way of ensuring we conform to the style guidelines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10475Michael Liao2013-03-01
| | | | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Disable vector registersJustin Holewinski2013-02-12
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski2012-11-29
| | | | | | | | computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski2012-11-14
| | | | | | | | | Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-25
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds a new NVPTX back-end to LLVM which supports code generation ↵Justin Holewinski2012-05-04
for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
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