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* [NVPTX] Add missing patterns for div.approx with immediate denominatorJustin Holewinski2014-01-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199746 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix handling of indirect callsJustin Holewinski2013-11-15
| | | | | | Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194810 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add missing patterns for i1 [s,u]int_to_fpJustin Holewinski2013-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187800 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix bug in stack code generation causes by MC conversionJustin Holewinski2013-08-06
| | | | | | | We do use a very small set of physical registers, so account for them in the virtual register encoding between MachineInstr and MC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187799 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Use approximate FP ops when unsafe-fp-math is used, and appendJustin Holewinski2013-07-22
| | | | | | .ftz to instructions if the nvptx-f32ftz attribute is set to "true" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186820 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add support for native SIGN_EXTEND_INREG where availableJustin Holewinski2013-07-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185330 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Select -1 instead of 1 when anyextend'ing i1 typesJustin Holewinski2013-06-28
| | | | | | This makes it more consistent with the ZeroOrNegativeOneBooleanContent flag git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185179 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add (1.0 / sqrt(x)) => rsqrt(x) generation when allowable by FP flagsJustin Holewinski2013-06-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185178 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add support for cttz/ctlz/ctpopJustin Holewinski2013-06-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185176 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Clean up comparison/select/convert patterns and factor out PTX ↵Justin Holewinski2013-06-28
| | | | | | | | instructions from their patterns Test case is no breakage git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185175 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is ↵Justin Holewinski2013-06-28
| | | | | | rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185174 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add infrastructure for vector loads/stores of parametersJustin Holewinski2013-06-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185171 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsicJustin Holewinski2013-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182394 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Disable vector registersJustin Holewinski2013-02-12
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds a new NVPTX back-end to LLVM which supports code generation ↵Justin Holewinski2012-05-04
for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
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