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* [PowerPC] Skeletal FastISel support for 64-bit PowerPC ELF.Bill Schmidt2013-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the first of many upcoming patches for PowerPC fast instruction selection support. This patch implements the minimum necessary for a functional (but extremely limited) FastISel pass. It allows the table-generated portions of the selector to be created and used, but in most cases selection will fall back to the DAG selector. None of the block terminator instructions are implemented yet, and most interesting instructions require some special handling. Therefore there aren't any new test cases with this patch. There will be quite a few tests coming with future patches. This patch adds the make/CMake support for the new code (including tablegen -gen-fast-isel) and creates the FastISel object for PPC64 ELF only. It instantiates the necessary virtual functions (TargetSelectInstruction, TargetMaterializeConstant, TargetMaterializeAlloca, tryToFoldLoadIntoMI, and FastLowerArguments), but of these, only TargetMaterializeConstant contains any useful implementation. This is present since the table-generated code requires the ability to materialize integer constants for some instructions. This patch has been tested by building and running the projects/test-suite code with -O0. All tests passed with the exception of a couple of long-running tests that time out using -O0 code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187399 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add assembler parserUlrich Weigand2013-05-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds assembler parser support to the PowerPC back end. The parser will run for any powerpc-*-* and powerpc64-*-* triples, but was tested only on 64-bit Linux. The supported syntax is intended to be compatible with the GNU assembler. The parser does not yet support all PowerPC instructions, but it does support anything that is generated by LLVM itself. There is no support for testing restricted instruction sets yet, i.e. the parser will always accept any instructions it knows, no matter what feature flags are given. Instruction operands will be checked for validity and errors generated. (Error handling in general could still be improved.) The patch adds a number of test cases to verify instruction and operand encodings. The tests currently cover all instructions from the following PowerPC ISA v2.06 Book I facilities: Branch, Fixed-point, Floating-Point, and Vector. Note that a number of these instructions are not yet supported by the back end; they are marked with FIXME. A number of follow-on check-ins will add extra features. When they are all included, LLVM passes all tests (including bootstrap) when using clang -cc1as as the system assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-14
| | | | | | | registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-27
| | | | | | | into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-24
| | | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement a basic MCCodeEmitter for PPC. This doesn't handleChris Lattner2010-11-15
| | | | | | | | | | | | | | | | | | fixups yet, and doesn't handle actually encoding operand values, but this is enough for llc -show-mc-encoding to show the base instruction encoding information, e.g.: mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00] stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00] Ltmp0: lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00] cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00] beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119116 91177308-0d34-0410-b5e6-96231b3b80d8
* stub out a powerpc MCInstPrinter implementation.Chris Lattner2010-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
* move PPCAsmPrinter into the main PPC library, like ARM and X86.Chris Lattner2010-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119054 91177308-0d34-0410-b5e6-96231b3b80d8
* make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.Chris Lattner2010-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94378 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop building RTTI information for *most* llvm libraries. NotableChris Lattner2010-01-22
| | | | | | | | | | | | | missing ones are libsupport, libsystem and libvmcore. libvmcore is currently blocked on bugpoint, which uses EH. Once it stops using EH, we can switch it off. This #if 0's out 3 unit tests, because gtest requires RTTI information. Suggestions welcome on how to fix this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94164 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetInfo libraries for all targets.Daniel Dunbar2009-07-15
| | | | | | | | | - Intended to match current TargetMachine implementations. - No facilities for linking these in yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75751 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed trailing whitespace from Makefiles.Misha Brukman2009-01-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61991 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct name for PPC codegen libraryAnton Korobeynikov2008-08-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54888 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out asmprinter out of ppcAnton Korobeynikov2008-08-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54887 91177308-0d34-0410-b5e6-96231b3b80d8
* remove attribution from lib Makefiles.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45415 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch PPC return lower to use an autogenerated CC description.Chris Lattner2007-03-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34940 91177308-0d34-0410-b5e6-96231b3b80d8
* don't dist internal readme'sChris Lattner2006-10-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31246 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the README files to the distribution.Reid Spencer2006-04-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27651 91177308-0d34-0410-b5e6-96231b3b80d8
* Plugin new subtarget backend into the build.Jim Laskey2005-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23870 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.tdChris Lattner2005-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
* ask for a dag iselChris Lattner2005-09-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23238 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove support for 64b PPC, it's been broken for a long time. It'll beNate Begeman2005-08-13
| | | | | | | back once a DAG->DAG ISel exists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22778 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify all of the targets built.Chris Lattner2004-12-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18985 91177308-0d34-0410-b5e6-96231b3b80d8
* Change Library Names Not To Conflict With Others When InstalledReid Spencer2004-10-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17286 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous blank lineMisha Brukman2004-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17180 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust to changes in Makefile.rulesReid Spencer2004-10-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17167 91177308-0d34-0410-b5e6-96231b3b80d8
* * Make a PPC32-specific code emitter because we have separate classes for 32-Misha Brukman2004-10-14
| | | | | | | | | | | and 64-bit code emitters that cannot share code unless we use virtual functions * Identify components being built by tablegen with more detail by assigning them to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16980 91177308-0d34-0410-b5e6-96231b3b80d8
* * Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared betweenMisha Brukman2004-09-05
| | | | | | | | | Darwin and AIX and is not 32- or 64-bit specific * Bring back PowerPC.td as a result, to make it use the `PowerPC' class name * Adjust Makefile accordingly git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16174 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite targets/rules to generate files for just PowerPC or PPC{32,64}Misha Brukman2004-08-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15862 91177308-0d34-0410-b5e6-96231b3b80d8
* Add generation of asm writer from tablegen files to MakefileNate Begeman2004-08-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15740 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate a code emitter for PowerPC as well, this will be used in the JIT.Misha Brukman2004-08-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15578 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify makefile by combining all TableGen dependencies into one variableMisha Brukman2004-08-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15527 91177308-0d34-0410-b5e6-96231b3b80d8
* Align dependencies so they don't hurt the eyes to look at themMisha Brukman2004-08-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15504 91177308-0d34-0410-b5e6-96231b3b80d8
* Make tablegen targets depend on PowerPCInstrFormats.td as wellMisha Brukman2004-08-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15500 91177308-0d34-0410-b5e6-96231b3b80d8
* Renamed files:Misha Brukman2004-07-27
| | | | | | | | * PowerPCReg.td => PowerPCRegisterinfo.td * PowerPCInstrs.td => PowerPCInstrInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15295 91177308-0d34-0410-b5e6-96231b3b80d8
* The generated instruction selector isn't (yet) functionalMisha Brukman2004-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14894 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert stuff that I didn't mean to checkinChris Lattner2004-07-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14844 91177308-0d34-0410-b5e6-96231b3b80d8
* Patches towards fixing PR341Chris Lattner2004-07-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14841 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial revisionMisha Brukman2004-06-21
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
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