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path: root/lib/Target/PowerPC/PPCInstrAltivec.td
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* Mark PPC MFTB and DST (and friends) as deprecatedHal Finkel2013-09-12
| | | | | | | | Use the new instruction deprecation feature to mark mftb (now replaced with mfspr) and dst (along with the other Altivec cache control instructions) as deprecated when targeting cores supporting at least ISA v2.03. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Add some missing V_SET0 patternsHal Finkel2013-07-11
| | | | | | | | | | We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for v8i16 (which occurs in the test case) or v16i8. The same was true for V_SETALLONES (so I added the associated patterns for those as well). Another bug found by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186108 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Make specialized AltiVec patterns isCodeGenOnlyUlrich Weigand2013-07-03
| | | | | | | | | | | | | A couple of AltiVec patterns are just specialized forms of the generic instruction pattern, and should therefore be marked isCodeGenOnly to avoid confusing the asm parser: VCFSX_0, VCTUXS_0, VCFUX_0, VCTSXS_0, and V_SETALLONES. Noticed by inspection of the generated PPCGenAsmMatcher.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185533 91177308-0d34-0410-b5e6-96231b3b80d8
* PowerPC: Use RegisterOperand instead of RegisterClass operandsUlrich Weigand2013-04-26
| | | | | | | | | | | | | | | | | | | In the default PowerPC assembler syntax, registers are specified simply by number, so they cannot be distinguished from immediate values (without looking at the opcode). This means that the default operand matching logic for the asm parser does not work, and we need to specify custom matchers. Since those can only be specified with RegisterOperand classes and not directly on the RegisterClass, all instructions patterns used by the asm parser need to use a RegisterOperand (instead of a RegisterClass) for all their register operands. This patch adds one RegisterOperand for each RegisterClass, using the same name as the class, just in lower case, and updates all instruction patterns to use RegisterOperand instead of RegisterClass operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180611 91177308-0d34-0410-b5e6-96231b3b80d8
* PowerPC: Fix encoding of vsubcuw and vsum4sbs instructionsUlrich Weigand2013-04-26
| | | | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Tests will be added together with the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180608 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Add a FIXME regarding the non-working fma+fneg Altivec patternHal Finkel2013-04-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178658 91177308-0d34-0410-b5e6-96231b3b80d8
* More direct types in PowerPC AltiVec intrinsics.Ulrich Weigand2013-04-03
| | | | | | | | | | | | This patch follows up on work done by Bill Schmidt in r178277, and replaces most of the remaining uses of VRRC in ISEL DAG patterns. The resulting .inc files are identical except for comments, so no change in code generation is expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178656 91177308-0d34-0410-b5e6-96231b3b80d8
* Use PPC reciprocal estimates with Newton iteration in fast-math modeHal Finkel2013-04-03
| | | | | | | | | | | | | | | | | | | When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
* Use direct types in most PowerPC Altivec instructions and patterns.Bill Schmidt2013-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | This follows up Ulrich Weigand's work in PPCInstrInfo.td and PPCInstr64Bit.td by doing the corresponding work for most of the Altivec patterns. I have not been able to do anything for the following classes of instructions: (1) Vector logicals. These don't have corresponding intrinsics and don't have a single obvious vector type. So far as I can tell I need to leave these as VRRC. Affected instructions are: VAND, VANDC, VNOR, VOR, VXOR, V_SET0. (2) Instructions that make use of vector shuffle. The selection code promotes all shuffles to v16i8, so any pattern that matches on a shuffle is constrained. I haven't found any way to make the patterns match on their natural types, so I plan to leave these as VRRC. Affected instructions are: VMRG*, VSPLTB, VSPLTH, VSPLTW, VPKUHUM, VPKUWUM. No change in behavior is anticipated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178277 91177308-0d34-0410-b5e6-96231b3b80d8
* PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand2013-03-26
| | | | | | | | | | | | | There remain a number of patterns that cannot (and should not) be handled by the asm parser, in particular all the Pseudo patterns. This commit marks those patterns as isCodeGenOnly. No change in generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178008 91177308-0d34-0410-b5e6-96231b3b80d8
* Protect PPC Altivec patterns with a predicateHal Finkel2013-03-15
| | | | | | | | | | | | In preparation for the addition of other SIMD ISA extensions (such as QPX) we need to make sure that all Altivec patterns are properly predicated on having Altivec support. No functionality change intended (one test case needed to be updated b/c it assumed that Altivec intrinsics would be supported without enabling Altivec support). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes the Altivec addend construction for the fused multiply-addAdhemerval Zanella2012-11-30
| | | | | | | | | | | | | | | | instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero result when resulting product is -0.0. The -0.0 vector addend to vmaddfp is generated by a creating a vector with full bits sets and then shifting each elements by 31-bits to the left, resulting in a vector of 0x80000000 (or -0.0 as float). The 'buildvec_canonicalize.ll' was adjusted to reflect this change and the 'vec_mul.ll' was complemented with the float vector multiplication test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168998 91177308-0d34-0410-b5e6-96231b3b80d8
* PowerPC: Lowering floor intrinsic for AltivecAdhemerval Zanella2012-11-15
| | | | | | | | | This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and llvm.nearbyint to Altivec instruction when using 4 single-precision float vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
* Add floating-point to and from integer conversionAdhemerval Zanella2012-10-08
| | | | | | | | This patch add altivec support for v4i32 to v4f32 and for v4f32 to v4i32 vector rounding conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165409 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert the PPC backend to use the new FMA infrastructure.Hal Finkel2012-06-22
| | | | | | | The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158955 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.Hal Finkel2012-04-01
| | | | | | | | | | | Loads and stores can have different pipeline behavior, especially on embedded chips. This change allows those differences to be expressed. Except for the 440 scheduler, there are no functionality changes. On the 440, the latency adjustment is only by one cycle, and so this probably does not affect much. Nevertheless, it will make a larger difference in the future and this removes a FIXME from the 440 itin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* fix up vnot matching, eliminating a dead pattern, correcting a couple ofChris Lattner2010-03-28
| | | | | | | | patterns that would never match because of bitcast, and eliminating use of vnot_conv. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99753 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bunch of ambiguous patterns which tblgen happens to infer typesChris Lattner2010-03-08
| | | | | | | for, due to a bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97953 91177308-0d34-0410-b5e6-96231b3b80d8
* PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec Eli Friedman2009-06-07
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73009 91177308-0d34-0410-b5e6-96231b3b80d8
* 2nd attempt, fixing SSE4.1 issues and implementing feedback from duncan.Nate Begeman2009-04-27
| | | | | | | | | | | | | | | | PR2957 ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70225 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 69952. Causes testsuite failures on linux x86-64.Rafael Espindola2009-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
* PR2957Nate Begeman2009-04-24
| | | | | | | | | | | | | | | ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes as the shuffle mask. A value of -1 represents UNDEF. In addition to eliminating the creation of illegal BUILD_VECTORS just to represent shuffle masks, we are better about canonicalizing the shuffle mask, resulting in substantially better code for some classes of shuffles. A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-28
| | | | | | Node to reflect semantics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-15
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some isStore flags that are now inferred automatically.Chris Lattner2008-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45652 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the 64-bit versions of the DS* Altivec instructions.Bill Wendling2007-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41717 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix arguments for some Altivec instructions. From SWB.Dale Johannesen2007-08-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40957 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix spelling of mtvscr and mfvscr.Dale Johannesen2007-08-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40908 91177308-0d34-0410-b5e6-96231b3b80d8
* Vector fneg must be expanded into fsub -0.0, X.Evan Cheng2007-07-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
* No more noResults.Evan Cheng2007-07-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-19
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* fix incorrect encoding of vminsw.Chris Lattner2007-02-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34351 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the implicit def instructions look like other instrs.Chris Lattner2006-07-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29174 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some now-unneeded casts from instruction patterns. With the castsChris Lattner2006-06-20
| | | | | | | removed, tblgen produces identical output to with them in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28867 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the CodeGen/PowerPC/buildvec_canonicalize.ll regression last night.Chris Lattner2006-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27908 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure that the new instructions selected have the right type. This fixesChris Lattner2006-04-20
| | | | | | | CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27868 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement a TODO: have the legalizer canonicalize a bunch of operations toChris Lattner2006-04-16
| | | | | | | | one type (v4i32) so that we don't have to write patterns for each type, and so that more CSE opportunities are exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27731 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for matching vnots with bit converted inputs. Most of these willChris Lattner2006-04-15
| | | | | | | go away when I start using evan's binop type canonicalizer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27725 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename get_VSPLI_elt -> get_VSPLTI_eltChris Lattner2006-04-12
| | | | | | | | | | Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each form, eliminating a bunch of Pat patterns in the .td file and allowing us to CSE stuff more aggressively. This implements PowerPC/buildvec_canonicalize.ll:VSPLTI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27614 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure that zero vectors are always v4i32, which forces them to CSE withChris Lattner2006-04-12
| | | | | | | each other. This implements CodeGen/PowerPC/vxor-canonicalize.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27609 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the interface to the predicate that determines if vsplti* can be used.Chris Lattner2006-04-08
| | | | | | | No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27536 91177308-0d34-0410-b5e6-96231b3b80d8
* Match vpku[hw]um(x,x).Chris Lattner2006-04-06
| | | | | | | Convert vsldoi(x,x) to work the same way other (x,x) cases work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27467 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for matching vmrg(x,x) patternsChris Lattner2006-04-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27463 91177308-0d34-0410-b5e6-96231b3b80d8
* Pattern match vmrg* instructions, which are now lowered by the CFE into ↵Chris Lattner2006-04-06
| | | | | | shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27457 91177308-0d34-0410-b5e6-96231b3b80d8
* Support pattern matching vsldoi(x,y) and vsldoi(x,x), which allows the f.e. toChris Lattner2006-04-06
| | | | | | | | lower it and LLVM to have one fewer intrinsic. This implements CodeGen/PowerPC/vec_shuffle.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27450 91177308-0d34-0410-b5e6-96231b3b80d8
* Compile the vpkuhum/vpkuwum intrinsics into vpkuhum/vpkuwum instead of intoChris Lattner2006-04-06
| | | | | | | vperm with a perm mask lvx'd from the constant pool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27448 91177308-0d34-0410-b5e6-96231b3b80d8
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