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path: root/lib/Target/PowerPC/PPCInstrFormats.td
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* implement the vsldoi intrinsic.Chris Lattner2006-03-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the JIT encoding of the VAForm_1 instructions, including vmaddfpChris Lattner2006-03-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark instructions that are cracked by the PPC970 decoder as such.Chris Lattner2006-03-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
* Several big changes:Chris Lattner2006-03-12
| | | | | | | | | | | | 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
* PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner2006-01-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25674 91177308-0d34-0410-b5e6-96231b3b80d8
* Pattern-match return. Includes gross hack!Nate Begeman2005-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for fmul node of type v4f32.Nate Begeman2005-12-14
| | | | | | | | | | | | | | | | | | | | | | | void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float> *%a ret void } Is selected to: _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v0, v0, v0, v1 stvx v0, r2, r3 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support patterns to many load and store instructions which willNate Begeman2005-12-09
| | | | | | | hopefully use patterns in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8
* Define BR in the .td file now that Evan made tblgen smarter.Chris Lattner2005-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24589 91177308-0d34-0410-b5e6-96231b3b80d8
* Represent the encoding of the SPR instructions as they actually are, soNate Begeman2005-11-29
| | | | | | | | that we can use the correct SPR numbers in the InstrInfo.td file. This is necessary to support VRsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24521 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the remainder of the AltiVec 4 x float instructions. FurtherNate Begeman2005-11-29
| | | | | | | | enhancements will be necessary to teach the code generator that since there is no fmul, it will have to do vmaddfp, adding +0.0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
* Small tweaks noticed while on the plane.Nate Begeman2005-11-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
* Some first bits of AltiVec stuff: Instruction Formats, Encodings, andNate Begeman2005-11-23
| | | | | | | | | | | Registers. Apologies to Jim if the scheduling info so far isn't accurate. There's a few more things like VRsave support that need to be finished up in my local tree before I can commit code that Does The Right Thing for turning 4 x float into the various altivec packed float instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow pseudos to have patterns, no functionality changeChris Lattner2005-10-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8
* Added InstrSchedClass to each of the PowerPC Instructions.Jim Laskey2005-10-19
| | | | | | | | Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
* Write patterns for the various shl and srl patterns that don't involveNate Begeman2005-10-19
| | | | | | | doing something clever. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
* Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitionsChris Lattner2005-10-14
| | | | | | | from the .td file that correspond to it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bunch of patterns for F64 FP ops, add some more integer opsChris Lattner2005-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
* add patterns for x?oris?Chris Lattner2005-09-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23268 91177308-0d34-0410-b5e6-96231b3b80d8
* add patterns to the addi/addis/mulli etc instructions. Define predicatesChris Lattner2005-09-08
| | | | | | | for matching signed 16-bit and shifted 16-bit ppc immediates git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23267 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for some new instructions, allowing the use of the ineg fragment.Chris Lattner2005-09-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23266 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AND/OR/XORChris Lattner2005-09-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23232 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some initial patterns to simple binary instructions, though theyChris Lattner2005-09-02
| | | | | | | | | | currently don't do anything. This elides patterns for binary operators that ping on the carry flag, since we don't model it yet. This patch also removes PPC::SUB, because it is dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23230 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix JIT encoding of conditional branchesNate Begeman2005-08-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23076 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix JIT encoding of ppc mfocrf instruction; the operands were reversedNate Begeman2005-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22707 91177308-0d34-0410-b5e6-96231b3b80d8
* switch over the rest of the formats that use RC to use isDOTChris Lattner2005-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21352 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert the XForm instrs and XSForm instruction over to use isDOTChris Lattner2005-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21351 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that the ppc64 and vmx operands of I are always 0, forward substituteChris Lattner2005-04-19
| | | | | | | them away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21350 91177308-0d34-0410-b5e6-96231b3b80d8
* convert over bform and iform instructionsChris Lattner2005-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert over DForm and DSForm instructionsChris Lattner2005-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert XLForm and XForm instructions over to use PPC64 when appropriate.Chris Lattner2005-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert XO XS and XFX forms to use isPPC64Chris Lattner2005-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn PPC64 and VMX into classes that can be added to instructions instead ofChris Lattner2005-04-19
| | | | | | | | bits that must be passed up the inheritance hierarchy. Convert MForm and AForm instructions over git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
* Change codegen for setcc to read the bit directly out of the conditionNate Begeman2005-04-18
| | | | | | | | | register. Added support in the .td file for the g5-specific variant of cr -> gpr moves that executes faster, but we currently don't generate it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the necessary support to codegen condition register logical ops withNate Begeman2005-04-14
| | | | | | | | register allocated condition registers. Make sure that the printed output is gas compatible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for allocation condition registersNate Begeman2005-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the previous patch, which I didn't mean to check in.Chris Lattner2005-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a minor bug (ORo didn't mark that it set CR0).Chris Lattner2005-04-11
| | | | | | | | | | | | | | | | | | | | | Refactor how . instructions are handled. In particular, instead of passing the RC flag all the way up the inheritance hierarchy, just make a new tblgen class 'DOT' which can be added to an instruction definition. For example, instead of this: -def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), -let Defs = [CR0] in -def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "and. $rA, $rS, $rB">; We now have this: +def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), "and $rA, $rS, $rB">; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of fsel, fixing olden/power, McCat/bisort and several others.Chris Lattner2004-11-25
| | | | | | | All of Olden passes now! :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18227 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of swari, fixing several programs, including Olden/mstChris Lattner2004-11-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18225 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few more tests by encoding the extsb and other XForm11 instructionsChris Lattner2004-11-24
| | | | | | | correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18200 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the encoding of ORi and other DForm4 instructions. This brings us toChris Lattner2004-11-24
| | | | | | | 36/42 SingleSource/UnitTests passing! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18199 91177308-0d34-0410-b5e6-96231b3b80d8
* Branch instructions explicitly represent CRx in them. bEcause of this, encodeChris Lattner2004-11-24
| | | | | | | them explicitly as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18193 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the encoding of OR, AND and many other instructionsChris Lattner2004-11-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18174 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove argtype and argcount magic, which was used by the old asmprinter.Chris Lattner2004-11-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18170 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of rlwinm?Chris Lattner2004-11-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18165 91177308-0d34-0410-b5e6-96231b3b80d8
* DForm_1, particularly used by store instructions, needs the immediate operand toMisha Brukman2004-10-23
| | | | | | | | be listed second as that is how the instructions are usually created (and is the correct asm syntax) so that it's assembled correctly from its constituents git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17183 91177308-0d34-0410-b5e6-96231b3b80d8
* There is only one field in an instruction, and that is `Inst', the final view ofMisha Brukman2004-10-14
| | | | | | | | the instruction binary format, all others are simply operands and should not have the `field' label git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16978 91177308-0d34-0410-b5e6-96231b3b80d8
* All PPC instructions are now auto-printedNate Begeman2004-09-04
| | | | | | | | 32 and 64 bit AsmWriters unified Darwin and AIX specific features of AsmWriter split out git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert remaining X-Form and Pseudo instructions over to asm writerNate Begeman2004-09-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16142 91177308-0d34-0410-b5e6-96231b3b80d8
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