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	Commit message (Collapse)	Author	Age
*	Split several PPC instruction classes.	Hal Finkel	2012-08-28
\| \| \| \| \| \| \| \| \| \| \| \| \|	Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
*	Split out the PPC instruction class IntSimple from IntGeneral.	Hal Finkel	2012-06-12
\| \| \| \| \| \| \|	On the POWER7, adds and logical operations can also be handled in the load/store pipelines. We'll call these IntSimple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
*	Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.	Hal Finkel	2012-04-01
\| \| \| \| \| \| \| \| \| \| \|	Loads and stores can have different pipeline behavior, especially on embedded chips. This change allows those differences to be expressed. Except for the 440 scheduler, there are no functionality changes. On the 440, the latency adjustment is only by one cycle, and so this probably does not affect much. Nevertheless, it will make a larger difference in the future and this removes a FIXME from the 440 itin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8
*	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵	Jia Liu	2012-02-18
\| \| \| \| \| \|	MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add support to model pipeline bypass / forwarding.	Evan Cheng	2010-09-28
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
*	Make processor FUs unique for given itinerary. This extends the limit of 32	Anton Korobeynikov	2010-04-18
\| \| \| \| \| \| \|	FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
*	Remove attribution from file headers, per discussion on llvmdev.	Chris Lattner	2007-12-29
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
*	Added InstrSchedClass to each of the PowerPC Instructions.	Jim Laskey	2005-10-19
\| \| \| \| \| \| \| \|	Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
*	Push processor descriptions to the top of target and add command line info.	Jim Laskey	2005-10-19
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23820 91177308-0d34-0410-b5e6-96231b3b80d8
*	Simple edits; remove unimplimented cases and clarify long haul SLU cases.	Jim Laskey	2005-10-18
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23788 91177308-0d34-0410-b5e6-96231b3b80d8
*	Checking in first round of scheduling tablegen files. Not tied in as yet.	Jim Laskey	2005-10-18
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23786 91177308-0d34-0410-b5e6-96231b3b80d8