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R600
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R600Instructions.td
Commit message (
Expand
)
Author
Age
*
R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ...
Tom Stellard
2013-05-10
*
R600: BFI_INT is a vector-only instruction
Tom Stellard
2013-05-03
*
R600: Add pattern for SHA-256 Ma function
Tom Stellard
2013-05-03
*
R600: Improve asmPrint of ALU clause
Vincent Lejeune
2013-05-02
*
R600: Prettier asmPrint of Alu
Vincent Lejeune
2013-05-02
*
R600: Use new tablegen syntax for patterns
Tom Stellard
2013-05-02
*
R600: use native for alu
Vincent Lejeune
2013-04-30
*
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
Vincent Lejeune
2013-04-30
*
R600: Add a Bank Swizzle operand
Vincent Lejeune
2013-04-30
*
R600: Turn TEX/VTX into native instructions
Vincent Lejeune
2013-04-30
*
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
Vincent Lejeune
2013-04-30
*
R600: Clean up instruction class definitions
Vincent Lejeune
2013-04-30
*
R600: Fix encoding of CF_END_{EG, R600} instructions
Tom Stellard
2013-04-29
*
R600: Use .AMDGPU.config section to emit stacksize
Vincent Lejeune
2013-04-23
*
R600: Add CF_END
Vincent Lejeune
2013-04-23
*
R600: Add pattern for the BFI_INT instruction
Tom Stellard
2013-04-19
*
R600: Make Export Instruction not duplicable
Vincent Lejeune
2013-04-17
*
R600: Export is emitted as a CF_NATIVE inst
Vincent Lejeune
2013-04-17
*
R600/SI: Add pattern for AMDGPUurecip
Michel Danzer
2013-04-10
*
R600: Control Flow support for pre EG gen
Vincent Lejeune
2013-04-08
*
R600: Add support for native control flow
Vincent Lejeune
2013-04-01
*
R600: Emit CF_ALU and use true kcache register.
Vincent Lejeune
2013-04-01
*
R600: Emit native instructions for tex
Vincent Lejeune
2013-03-31
*
R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics
Michel Danzer
2013-03-22
*
R600/SI: add float vector types
Christian Konig
2013-03-18
*
R600: Fix JUMP handling so that MachineInstr verification can occur
Vincent Lejeune
2013-03-11
*
R600: Improve custom lowering of select_cc
Tom Stellard
2013-03-08
*
R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.
Vincent Lejeune
2013-03-05
*
R600: CONST_ADDRESS node is not marked as mayLoad anymore
Vincent Lejeune
2013-03-05
*
R600: Use MUL_IEEE for trig/fdiv intrinsic
Vincent Lejeune
2013-03-05
*
R600: Add support for indirect addressing of non default const buffer
Vincent Lejeune
2013-03-05
*
R600: Fix for Unigine when MachineSched is enabled
Tom Stellard
2013-02-21
*
R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
Vincent Lejeune
2013-02-18
*
R600: Support for TBO
Vincent Lejeune
2013-02-18
*
R600: Export instructions are no longer terminator
Vincent Lejeune
2013-02-14
*
R600: Fold zero/one in export instructions
Vincent Lejeune
2013-02-14
*
R600: Add support for 128-bit parameters
Tom Stellard
2013-02-13
*
R600: Fix regression with shadow array sampler on pre-SI GPUs.
Michel Danzer
2013-02-12
*
Test Commit - Remove some trailing whitespace in R600Instructions.td
Vincent Lejeune
2013-02-10
*
R600/SI: Use proper instructions for array/shadow samplers.
Tom Stellard
2013-02-07
*
R600: Consolidate sub register indices.
Tom Stellard
2013-02-07
*
R600: Add support for SET*_DX10 instructions
Tom Stellard
2013-02-07
*
R600: Fix assembly name for SETGT_INT
Tom Stellard
2013-02-07
*
R600: Support for indirect addressing v4
Tom Stellard
2013-02-06
*
Don't use MRI liveouts in R600.
Jakob Stoklund Olesen
2013-02-05
*
R600: improve inputs/interpolation handling
Tom Stellard
2013-02-05
*
R600: Make store_dummy intrinsic more general by passing export type
Tom Stellard
2013-01-31
*
R600: Add a llvm.R600.store.swizzle intrinsics
Tom Stellard
2013-01-23
*
R600: Simplify stream outputs intrinsic
Tom Stellard
2013-01-23
*
R600: rework handling of the constants
Tom Stellard
2013-01-23
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