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* Merging r196168:Tom Stellard2014-04-08
| | | | | | | | | | | ------------------------------------------------------------------------ r196168 | rafael.espindola | 2013-12-02 18:04:51 -0500 (Mon, 02 Dec 2013) | 2 lines Convert two char* that are only ever used as booleans to bool. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205764 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203818:Tom Stellard2014-03-24
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r203818 | thomas.stellard | 2014-03-13 10:13:04 -0700 (Thu, 13 Mar 2014) | 7 lines R600: LDS instructions shouldn't implicitly define OQAP LDS instructions are pseudo instructions which model the OQAP defs and uses within a single instruction. This fixes a hang in the opencv MedianFilter tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204650 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203281:Tom Stellard2014-03-24
| | | | | | | | | | | | ------------------------------------------------------------------------ r203281 | thomas.stellard | 2014-03-07 12:12:39 -0800 (Fri, 07 Mar 2014) | 4 lines R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204649 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201097:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r201097 | thomas.stellard | 2014-02-10 08:58:30 -0800 (Mon, 10 Feb 2014) | 9 lines R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204648 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201096:Tom Stellard2014-03-24
| | | | | | | | | | | | | ------------------------------------------------------------------------ r201096 | thomas.stellard | 2014-02-10 08:58:27 -0800 (Mon, 10 Feb 2014) | 6 lines R600/SI: Only use S_WQM_B64 in pixel shaders This doesn't change any functionality, since we only have two shader types (compute and pixel) that use local memory. We're just changing the logic to match the documentation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204647 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200830:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200830 | michel.daenzer | 2014-02-05 01:48:05 -0800 (Wed, 05 Feb 2014) | 8 lines R600/SI: Add pattern for zero-extending i1 to i32 Fixes opencl-example if_* tests with radeonsi. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469 Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204646 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200776:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200776 | thomas.stellard | 2014-02-04 09:18:43 -0800 (Tue, 04 Feb 2014) | 9 lines R600/SI: Expand i1 BR_CC This fixes a crashes in the OpenCV test suite and also the scrypt kernel in bfgminer. I was unable to come up with a reduced test case for this. https://bugs.freedesktop.org/show_bug.cgi?id=72785 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204645 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200775:Tom Stellard2014-03-24
| | | | | | | | | | | | | ------------------------------------------------------------------------ r200775 | thomas.stellard | 2014-02-04 09:18:42 -0800 (Tue, 04 Feb 2014) | 5 lines R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopies There is no lit test for this, because it would be too big and complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204644 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200743:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200743 | michel.daenzer | 2014-02-03 23:12:38 -0800 (Mon, 03 Feb 2014) | 11 lines R600/SI: Fix fneg for 0.0 V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204643 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200283:Tom Stellard2014-03-24
| | | | | | | | | | | | | ------------------------------------------------------------------------ r200283 | michel.daenzer | 2014-01-27 19:01:16 -0800 (Mon, 27 Jan 2014) | 6 lines R600/SI: Add pattern for truncating i32 to i1 Fixes half a dozen piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204642 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199919:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r199919 | thomas.stellard | 2014-01-23 10:49:34 -0800 (Thu, 23 Jan 2014) | 10 lines R600: Remove successive JUMP in AnalyzeBranch when AllowModify is true This fixes a crash in the OpenCV OpenCL test suite. There is no lit test for this, because the test would be very large and could easily be invalidated by changes to the scheduler or other parts of the compiler. Patch by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204641 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199918:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r199918 | thomas.stellard | 2014-01-23 10:49:33 -0800 (Thu, 23 Jan 2014) | 8 lines R600: Disable the BFE pattern This pattern uses an SDNodeXForm, which isn't being emitted for some reason. I can get it to work by attaching the PatLeaf that has the XForm to the argument in the output pattern, but this results in an immediate being used in a register operand, which the backend can't handle yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204640 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199917:Tom Stellard2014-03-24
| | | | | | | | | | | | | ------------------------------------------------------------------------ r199917 | thomas.stellard | 2014-01-23 10:49:31 -0800 (Thu, 23 Jan 2014) | 6 lines R600: Correctly handle vertex fetch clauses the precede ENDIFs The control flow finalizer would sometimes use an ALU_POP_AFTER instruction before the vetex fetch clause instead of using a POP instruction after it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204639 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r202336:Tom Stellard2014-03-24
| | | | | | | | | | | ------------------------------------------------------------------------ r202336 | michel.daenzer | 2014-02-26 17:47:02 -0800 (Wed, 26 Feb 2014) | 4 lines R600/SI: Allow SI_KILL for geometry shaders Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204638 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200196:Tom Stellard2014-03-24
| | | | | | | | | | | ------------------------------------------------------------------------ r200196 | michel.daenzer | 2014-01-26 23:20:51 -0800 (Sun, 26 Jan 2014) | 4 lines R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204637 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200195:Tom Stellard2014-03-24
| | | | | | | | | | | ------------------------------------------------------------------------ r200195 | michel.daenzer | 2014-01-26 23:20:44 -0800 (Sun, 26 Jan 2014) | 4 lines R600/SI: Add intrinsic for S_SENDMSG instruction Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204636 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195881:Bill Wendling2013-12-01
| | | | | | | | | | | | | ------------------------------------------------------------------------ r195881 | tstellar | 2013-11-27 13:23:39 -0800 (Wed, 27 Nov 2013) | 3 lines R600: Expand vector FABS NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196000 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195879:Bill Wendling2013-12-01
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195879 | tstellar | 2013-11-27 13:23:29 -0800 (Wed, 27 Nov 2013) | 6 lines R600/SI: Use SGPR_32 register class for 32-bit SMRD outputs Writing to the M0 register from an SMRD instruction hangs the GPU, so we need to use the SGPR_32 register class, which does not include M0. NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195999 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195878:Bill Wendling2013-12-01
| | | | | | | | | | | | | ------------------------------------------------------------------------ r195878 | tstellar | 2013-11-27 13:23:20 -0800 (Wed, 27 Nov 2013) | 3 lines R600: Add support for ISD::FROUND NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195998 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195514:Bill Wendling2013-11-25
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195514 | tstellar | 2013-11-22 15:07:58 -0800 (Fri, 22 Nov 2013) | 6 lines R600/SI: Fixing handling of condition codes We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195609 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195399:Bill Wendling2013-11-22
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195399 | tstellar | 2013-11-21 16:41:08 -0800 (Thu, 21 Nov 2013) | 10 lines R600: Implement TargetInstrInfo::isLegalToSplitMBBAt() Splitting a basic block will create a new ALU clause, so we need to make sure we aren't moving uses of registers that are local to their current clause into a new one. I had a test case for this, but unfortunately unrelated schedule changes invalidated it, and I wasn't been able to come up with another one. NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195415 91177308-0d34-0410-b5e6-96231b3b80d8
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-19
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-18
| | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-18
| | | | | | | No other SGPR operands are allowed, so if VCC is used, move the other to a VGPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-18
| | | | | | | | Test doesn't actually check the output. I need to fix add i64 being matched for the addressing calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Specify SSrc operandsMatt Arsenault2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195039 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: addc / adde i32 are legalMatt Arsenault2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195038 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Match addc to S_ADD_U32.Matt Arsenault2013-11-18
| | | | | | The carry always goes to SCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195037 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32Matt Arsenault2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195036 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Specify S_ADD/S_SUB set SCC and add is commutableMatt Arsenault2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195035 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-18
| | | | | | | When replacing scalar operations with vector, the wrong implicit output register was used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Enable the IR structurizer by defaultTom Stellard2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-18
| | | | | | | The ifPatternMatch() function was not correctly reporting the number of matches in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195030 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a SubtargetFeatture for disabling the ifcvt pass.Tom Stellard2013-11-18
| | | | | | This is useful when writing test cases for the AMDIL structurizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use lower-case for EnableIRStructurizer featureTom Stellard2013-11-18
| | | | | | | llc converts all values passed to -mattr= to lowercase, so this enables us to toggle this feature when using llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195028 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r194865 and r194874.Alexey Samsonov2013-11-18
| | | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194927 91177308-0d34-0410-b5e6-96231b3b80d8
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-15
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
* Make method staticMatt Arsenault2013-11-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194858 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-15
| | | | | | This fixes a crash with GNOME settings manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194836 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-15
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add processor type for HawaiiTom Stellard2013-11-14
| | | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194752 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Remove redundant legalizeOperands callMatt Arsenault2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194749 91177308-0d34-0410-b5e6-96231b3b80d8
* Add #include raw_ostream.h in lib/Target/R600/SIFixSGPRCopies.cppHans Wennborg2013-11-14
| | | | | | This was casuing my release+asserts build on Windows to fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194747 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Specify S_ADDK/S_MULK set SCC and are commutableMatt Arsenault2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194738 91177308-0d34-0410-b5e6-96231b3b80d8
* Indentation fixesMatt Arsenault2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194688 91177308-0d34-0410-b5e6-96231b3b80d8
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