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* R600: Implement 64bit SRLJan Vesely2014-06-18
* R600: Implement 64bit SHLJan Vesely2014-06-18
* R600/SI: Make sure target flags are set on pseudo VOP3 instructionsTom Stellard2014-06-17
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-17
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-17
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-17
* R600/SI: Add a pattern for llvm.AMDGPU.barrier.globalTom Stellard2014-06-17
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-17
* R600/SI: Re-initialize the m0 register after using it for indirect addressingTom Stellard2014-06-17
* Fix copy paste errorMatt Arsenault2014-06-15
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-15
* R600: Fix assert on vector sdivMatt Arsenault2014-06-15
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-15
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-15
* R600: Report that integer division is expensive.Matt Arsenault2014-06-15
* R600: Remove dead codeMatt Arsenault2014-06-15
* Fix typoMatt Arsenault2014-06-14
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-14
* R600: Use address space enum instead of valueMatt Arsenault2014-06-14
* R600: Cleanup some old AMDIL stuff.Matt Arsenault2014-06-13
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-13
* R600: Don't call setOperationAction with things that aren't opcodes.Matt Arsenault2014-06-13
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-13
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-13
* R600: Drop use of cached TargetMachine in R600InstrInfo.cppTom Stellard2014-06-13
* R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cppTom Stellard2014-06-13
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-12
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-12
* R600: Set correct InstrItinClass for instructions using *Helper classesTom Stellard2014-06-11
* R600: BCNT_INT is a vector only instructionTom Stellard2014-06-11
* R600/SI: Fix bitcast between v2i32 and f64Matt Arsenault2014-06-11
* R600/SI: Update place using old subtarget predicateMatt Arsenault2014-06-11
* R600/SI: Add common 64-bit LDS atomicsMatt Arsenault2014-06-11
* R600/SI: Add instruction definitions for 64-bit LDS atomicsMatt Arsenault2014-06-11
* R600/SI: Add 32-bit LDS atomic cmpxchgMatt Arsenault2014-06-11
* R600/SI: Use LDS atomic inc / decMatt Arsenault2014-06-11
* R600/SI: Add other LDS atomic operationsMatt Arsenault2014-06-11
* R600/SI: Add instruction definitions for more LDS opsMatt Arsenault2014-06-11
* R600/SI: Fix backwards names for local atomic instructions.Matt Arsenault2014-06-11
* R600/SI: Refactor local atomics.Matt Arsenault2014-06-11
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-11
* R600/SI: Fix selection failure on scalar_to_vectorMatt Arsenault2014-06-11
* Try to fix the msvc build.Rafael Espindola2014-06-11
* Use cast instead of assert + dyn_castMatt Arsenault2014-06-11
* R600: Add helper functions.Matt Arsenault2014-06-11
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-10
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-10
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-10
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-10
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-10
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