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path: root/lib/Target/SystemZ/SystemZInstrFP.td
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* [SystemZ] Rename subregs and add subreg_h32Richard Sandiford2013-09-30
| | | | | | | | | | | | | | Use subreg_hNN and subreg_lNN for the high and low NN bits of a register. List the low registers first, so that subreg_l32 also means the low 32 bits of a 128-bit register. Floats are stored in the upper 32 bits of a 64-bit register, so they should use subreg_h32 rather than subreg_l32. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Tweak integer comparison codeRichard Sandiford2013-09-06
| | | | | | | | | | | | | | | | | | | | The architecture has many comparison instructions, including some that extend one of the operands. The signed comparison instructions use sign extensions and the unsigned comparison instructions use zero extensions. In cases where we had a free choice between signed or unsigned comparisons, we were trying to decide at lowering time which would best fit the available instructions, taking things like extension type into account. The code to do that was getting increasingly hairy and was also making some bad decisions. E.g. when comparing the result of two LLCs, it is better to use CR rather than CLR, since CR can be fused with a branch while CLR can't. This patch removes the lowering code and instead adds an operand to integer comparisons to say whether signed comparison is required, whether unsigned comparison is required, or whether either is OK. We can then leave the choice of instruction up to the normal isel code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-05
| | | | | | | | For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Extend memcpy and memset support to all constant lengthsRichard Sandiford2013-08-27
| | | | | | | | | | | | | | | Lengths up to a certain threshold (currently 6 * 256) use a series of MVCs. Lengths above that threshold use a loop to handle X*256 bytes followed by a single MVC to handle the excess (if any). This loop will also be needed in future when support for variable lengths is added. Because the same tablegen classes are used to define MVC and CLC, the patch also has the side-effect of defining a pseudo loop instruction for CLC. That instruction isn't used yet (and wouldn't be handled correctly if it were). I'm planning to use it soon though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189331 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use FI[EDX]BRA for codegenRichard Sandiford2013-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188895 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add FI[EDX]BRARichard Sandiford2013-08-21
| | | | | | | | These are extensions of the existing FI[EDX]BR instructions, but use a spare bit to suppress inexact conditions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188894 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add a definition of the IPM instructionRichard Sandiford2013-08-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188161 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Optimize floating-point comparisons with zeroRichard Sandiford2013-08-07
| | | | | | | | | | This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187883 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add floating-point load-and-test instructionsRichard Sandiford2013-08-07
| | | | | | | These instructions can also be used as comparisons with zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use MVC for simple load/store pairsRichard Sandiford2013-07-09
| | | | | | | | | | | | | Look for patterns of the form (store (load ...), ...) in which the two locations are known not to partially overlap. (Identical locations are OK.) These sequences are better implemented by MVC unless either the load or the store could use RELATIVE LONG instructions. The testcase showed that we weren't using LHRL and LGHRL for extload16, only sextloadi16. The patch fixes that too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185919 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Fold more spillsRichard Sandiford2013-07-03
| | | | | | | | | | | | | | | | Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add conditional store patternsRichard Sandiford2013-06-27
| | | | | | | | | | | | | | | | | | | | | | Add pseudo conditional store instructions, so that we use: branch foo: store foo: instead of: load branch foo: move foo: store z196 has real 32-bit and 64-bit conditional stores, but we don't use any z196 instructions yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185065 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rename PSW to CCRichard Sandiford2013-05-22
| | | | | | | | | | | Addresses a review comment from Ulrich Weigand. No functional change intended. I'm not sure whether the old TODO that this patch touches still holds, but that's something we'd get to when adding a targetted scheduling description. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182474 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add back endUlrich Weigand2013-05-06
| | | | | | | | | | | | | | | | This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the SystemZ backend.Dan Gohman2011-10-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isTwoAddress from SystemZ.Eric Christopher2010-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106467 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve systemz to model cmp and ucmp nodes as returningChris Lattner2010-03-28
| | | | | | | their flags correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99738 91177308-0d34-0410-b5e6-96231b3b80d8
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-29
| | | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
* Update SystemZ to use PSW following the way x86 uses EFLAGS. BesidesDan Gohman2009-10-28
| | | | | | | | | | | | eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen change. This unfortunately requires SystemZ to switch to the list-burr scheduler, in order to handle the physreg defs properly, however that's what LLVM has available at this time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fcopysign instructionsAnton Korobeynikov2009-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79664 91177308-0d34-0410-b5e6-96231b3b80d8
* All FP instructions have 12 bit memory displacement fieldAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76058 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction mnemonics for some fp_to_sint operationsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76048 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle bitconvertsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76042 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit proper rounding mode for fp_to_sintAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76037 91177308-0d34-0410-b5e6-96231b3b80d8
* Make FP zero to be legal FP immediate via LOAD ZEROAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76034 91177308-0d34-0410-b5e6-96231b3b80d8
* Loads are not two-address in any wayAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76033 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LOAD NEGATIVE instructionAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76032 91177308-0d34-0410-b5e6-96231b3b80d8
* LOAD COMPLEMENT instruction is not really two-addrAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76031 91177308-0d34-0410-b5e6-96231b3b80d8
* Add multiple add/sub instructionsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76030 91177308-0d34-0410-b5e6-96231b3b80d8
* Proper FP extloadsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76028 91177308-0d34-0410-b5e6-96231b3b80d8
* Add proper PWS impdef'sAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76027 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate FP select_cc to dag insertersAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76026 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement fp_to_sintAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76025 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fabsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fnegAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76022 91177308-0d34-0410-b5e6-96231b3b80d8
* More sint_to_fp stuffAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76020 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bunch of FP instructionsAnton Korobeynikov2009-07-16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76019 91177308-0d34-0410-b5e6-96231b3b80d8
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