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path: root/lib/Target/SystemZ/SystemZInstrInfo.td
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* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-15
| | | | | | | Thanks to Ulrich Weigand for noticing that this instruction was missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Remove bogus isAsmParserOnlyRichard Sandiford2013-05-14
| | | | | | | | | | | Marking instructions as isAsmParserOnly stops them from being disassembled. However, in cases where separate asm and codegen versions exist, we actually want to disassemble to the asm ones. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181772 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add back endUlrich Weigand2013-05-06
| | | | | | | | | | | | | | | | This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the SystemZ backend.Dan Gohman2011-10-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-14
| | | | | | | | | | TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix imm printing for logical instructions.Anton Korobeynikov2011-02-01
| | | | | | Patch by Brian G. Lucas! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124679 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isTwoAddress from SystemZ.Eric Christopher2010-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106467 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndicesJakob Stoklund Olesen2010-05-28
| | | | | | | | | | were overspecified when inheriting sub-subregisters, for instance: R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit. This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve systemz to model cmp and ucmp nodes as returningChris Lattner2010-03-28
| | | | | | | their flags correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99738 91177308-0d34-0410-b5e6-96231b3b80d8
* set SDNPVariadic on nodes throughout the rest of the targets thatChris Lattner2010-03-19
| | | | | | | need them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a type compatibility bug. imm is i32 in the input Chris Lattner2010-03-08
| | | | | | | pattern, not i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97956 91177308-0d34-0410-b5e6-96231b3b80d8
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-29
| | | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
* Update SystemZ to use PSW following the way x86 uses EFLAGS. BesidesDan Gohman2009-10-28
| | | | | | | | | | | | eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen change. This unfortunately requires SystemZ to switch to the list-burr scheduler, in order to handle the physreg defs properly, however that's what LLVM has available at this time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85357 91177308-0d34-0410-b5e6-96231b3b80d8
* Some dummy cost model for s390x:Anton Korobeynikov2009-08-22
| | | | | | | | | - Prefer short-imm instructions over ext-imm, when possible - Prefer Z10 instructions over Z9, when possible This hopefully should fix some dejagnu test fails on solaris git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79741 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo :(Anton Korobeynikov2009-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79657 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct instruction names for subtract-with-borrowAnton Korobeynikov2009-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79656 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert bswap test to filecheck, add more test entries & convert stuff to ↵Anton Korobeynikov2009-08-05
| | | | | | filecheck git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78212 91177308-0d34-0410-b5e6-96231b3b80d8
* Add memory versions of some instructions.Anton Korobeynikov2009-08-05
| | | | | | Patch by Neale Ferguson! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78203 91177308-0d34-0410-b5e6-96231b3b80d8
* Add carry producing / using versions of add / subAnton Korobeynikov2009-07-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76316 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide expansion for ct* intrinsicsAnton Korobeynikov2009-07-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76311 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporary disable 16 bit bswapAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76063 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction formats and few opcodesAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76062 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bswap patternsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76061 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide crazy pseudos for regpairs spills / reloadsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76060 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the commit, it just hides the real bugAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76045 91177308-0d34-0410-b5e6-96231b3b80d8
* Out GR128 regclass is not a 'real' i128 one.Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76044 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle bitconvertsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76042 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension ↵Anton Korobeynikov2009-07-16
| | | | | | side effects git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76035 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle FP callee-saved regsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76029 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement all comparisonsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76017 91177308-0d34-0410-b5e6-96231b3b80d8
* Add constpool lowering / printingAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76016 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix fallout from prev. patchAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76012 91177308-0d34-0410-b5e6-96231b3b80d8
* Use divide single for 32 bit signed dividesAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76010 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement 'large' PIC modelAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76006 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement shifts properly (hopefilly - finally!)Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundand register moveAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76004 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly handle divides. As a bonus - implement memory versions of them.Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix epic fail: full-width muls are not commutable. This unbreaks bunch of ↵Anton Korobeynikov2009-07-16
| | | | | | stuff from SingleSource/Benchmarks/Stanford git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76002 91177308-0d34-0410-b5e6-96231b3b80d8
* 32 bit rotate is not twoaddr instructionAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76001 91177308-0d34-0410-b5e6-96231b3b80d8
* 32 bit shifts have only 12 bit displacementsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak indirect branchesAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75997 91177308-0d34-0410-b5e6-96231b3b80d8
* All calls clobbers R14Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75994 91177308-0d34-0410-b5e6-96231b3b80d8
* Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 12 bit displacementsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
* Add jump tablesAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8
* Exapnd br_jt into indirect branch. Provide pattern for indirect branches.Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75983 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement 64 bit immediatesAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75982 91177308-0d34-0410-b5e6-96231b3b80d8
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