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* Merging r196267:Richard Sandiford2013-12-03
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r196267 | rsandifo | 2013-12-03 11:01:54 +0000 (Tue, 03 Dec 2013) | 12 lines [SystemZ] Fix choice of known-zero mask in insertion optimization The backend converts 64-bit ORs into subreg moves if the upper 32 bits of one operand and the low 32 bits of the other are known to be zero. It then tries to peel away redundant ANDs from the upper 32 bits. Since AND masks are canonicalized to exclude known-zero bits, the test ORs the mask and the known-zero bits together before checking for redundancy. The problem was that it was using the wrong node when checking for known-zero bits, so could drop ANDs that were still needed. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196268 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195731:Richard Sandiford2013-11-26
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195731 | rsandifo | 2013-11-26 10:53:16 +0000 (Tue, 26 Nov 2013) | 7 lines [SystemZ] Fix incorrect use of RISBG for a zero-extended right shift We would wrongly transform the testcase into the equivalent of an AND with 1. The problem was that, when testing whether the shifted-in bits of the right shift were significant, we used the width of the final zero-extended result rather than the width of the shifted value. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195736 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195473:Richard Sandiford2013-11-22
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195473 | rsandifo | 2013-11-22 17:28:28 +0000 (Fri, 22 Nov 2013) | 10 lines [SystemZ] Fix TMHH and TMHL usage for z10 with -O0 I've no idea why I decided to handle TMxx differently from all the other high/low logic operations, but it was a stupid thing to do. The high registers aren't available as separate 32-bit registers on z10, so subreg_h32 can't be used on a GR64 there. I've normally been testing with z196 and with -O3 and so hadn't noticed this until now. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195474 91177308-0d34-0410-b5e6-96231b3b80d8
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-19
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r194865 and r194874.Alexey Samsonov2013-11-18
| | | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-15
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add the general form of BCRRichard Sandiford2013-11-13
| | | | | | | At the moment this is just the MC support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Handle vectors in getSetCCResultTypeRichard Sandiford2013-11-06
| | | | | | | | I don't have a standalone testcase for this, but it should allow r193676 to be reapplied. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194148 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Automatically detect zEC12 and z196 hostsRichard Sandiford2013-10-31
| | | | | | | | | | | As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
* The AsmPrinter has a Mangler. Use it.Rafael Espindola2013-10-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193617 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Set usaAA to trueRichard Sandiford2013-10-28
| | | | | | | | | | | | | | | | | useAA significantly improves the handling of vector code that has TBAA information attached. It also helps other cases, as shown by the testsuite changes here. The only real downside I've seen is that it interferes with MergeConsecutiveStores. The problem is that that optimization works top down, starting at the first store in the chain, and looks for cases where the chain result is only used by a single related store. These related stores don't alias, so useAA will have rewritten all the later stores to use a different chain input (typically the same one as the first store). I think the advantages outweigh the disadvantages though, so for now I've just disabled alias analysis for the unaligned-01.ll test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193521 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Handle extensions in RxSBG optimizationsRichard Sandiford2013-10-16
| | | | | | | | The input to an RxSBG operation can be narrower as long as the upper bits are don't care. This fixes a FIXME added in r192783. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192790 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve handling of SETCCRichard Sandiford2013-10-16
| | | | | | | | | We previously used the default expansion to SELECT_CC, which in turn would expand to "LHI; BRC; LHI". In most cases it's better to use an IPM-based sequence instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192784 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-16
| | | | | | We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use A(G)SI when spilling the target of a constant additionRichard Sandiford2013-10-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192681 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing #include's to cctype when using isdigit/alpha/etc.Will Dietz2013-10-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192519 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-08
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add comparisons of high words and memoryRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add comparisons of large immediates using high wordsRichard Sandiford2013-10-01
| | | | | | | | There are no corresponding patterns for small immediates because they would prevent the use of fused compare-and-branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191775 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add immediate addition involving high wordsRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191774 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Extend test-under-mask support to high GR32sRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Extend 32-bit RISBG optimizations to high wordsRichard Sandiford2013-10-01
| | | | | | | | This involves using RISB[LH]G, whereas the equivalent z10 optimization uses RISBG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191770 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high wordsRichard Sandiford2013-10-01
| | | | | | | As the comment says, we always want to use STOC for 32-bit stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191767 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and aboveRichard Sandiford2013-10-01
| | | | | | | | | Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR transfers are full-register transfers. This patch optimizes GPR<->FPR float transfers when the high word of a GPR is directly accessible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191764 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Allow integer AND involving high wordsRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191762 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Allow integer XOR involving high wordsRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191759 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Allow integer OR involving high wordsRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191755 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Allow integer insertions with a high-word destinationRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191753 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Allow selects with a high-word destinationRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191751 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add patterns to load a constant into a high word (IIHF)Richard Sandiford2013-10-01
| | | | | | | | Similar to low words, we can use the shorter LLIHL and LLIHH if it turns out that the other half of the GR64 isn't live. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191750 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add register zero extensions involving at least one high wordRichard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191746 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add truncating high-word stores (STCH and STHH)Richard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191743 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)Richard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191742 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add sign-extending high-word loads (LBH and LHH)Richard Sandiford2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use upper words of GR64s for codegenRichard Sandiford2013-10-01
| | | | | | | | | | | | | | | This just adds the basics necessary for allocating the upper words to virtual registers (move, load and store). The move support is parameterised in a way that makes it easy to handle zero extensions, but the associated zero-extend patterns are added by a later patch. The easiest way of testing this seemed to be add a new "h" register constraint for high words. I don't expect the constraint to be useful in real inline asms, but it should work, so I didn't try to hide it behind an option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Reapply: Add definitions of LFH and STFHRichard Sandiford2013-10-01
| | | | | | | | Originally committed as r191661, but reverted because it changed the matching order of comparisons on some hosts. That should have been fixed by r191735. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191738 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Revert r191661: Add definitions of LFH and STFHRichard Sandiford2013-09-30
| | | | | | | | | For some reason, adding definitions for these load and store instructions changed whether some of the build bots matched comparisons as signed or unsigned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191663 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add definitions of LFH and STFHRichard Sandiford2013-09-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191661 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford2013-09-30
| | | | | | | | | | The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rename subregs and add subreg_h32Richard Sandiford2013-09-30
| | | | | | | | | | | | | | Use subreg_hNN and subreg_lNN for the high and low NN bits of a register. List the low registers first, so that subreg_l32 also means the low 32 bits of a 128-bit register. Floats are stored in the upper 32 bits of a 64-bit register, so they should use subreg_h32 rather than subreg_l32. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add change missing from previous commitRichard Sandiford2013-09-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191656 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rename 32-bit GPR registersRichard Sandiford2013-09-30
| | | | | | | | | I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rein back the use of block operationsRichard Sandiford2013-09-27
| | | | | | | | | | | | | | | The backend tries to use block operations like MVC, NC, OC and XC for simple scalar operations. For correctness reasons, it rejects any case in which the regions might partially overlap. However, for performance reasons, it should also reject cases where the regions might be equal, since the instruction might then not use the fast path. This fixes a performance regression seen in bzip2. We may want to limit the optimisation even more in future, or even remove it entirely, but I'll try with this for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve handling of PC-relative addressesRichard Sandiford2013-09-27
| | | | | | | | | | | | | | | The backend previously folded offsets into PC-relative addresses whereever possible. That's the right thing to do when the address can be used directly in a PC-relative memory reference (using things like LRL). But if we have a register-based memory reference and need to load the PC-relative address separately, it's better to use an anchor point that could be shared with other accesses to the same area of the variable. Fixes a FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.Richard Sandiford2013-09-25
| | | | | | | | | Another patch to avoid duplication of encoding information. Things like NILF, NILL and NILH are used as both 32-bit and 64-bit instructions. Here the 64-bit versions are defined as aliases of the 32-bit ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191369 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Define the call instructions as pseudo aliases.Richard Sandiford2013-09-25
| | | | | | | | | Similar to r191364, but for calls. This patch also removes the shortening of BRASL to BRAS within a TU. Doing that was a bit controversial internally, since there's a strong expectation with the z assembler that WYWIWYG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191366 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use subregs for 64-bit truncating storesRichard Sandiford2013-09-25
| | | | | | | | | Another patch to reduce the duplication of encoding information. Rather than define separate patterns for truncating 64-bit stores, use the 32-bit stores with a subreg. No behavioral changed intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191365 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Define the return instruction as a pseudo alias of BRRichard Sandiford2013-09-25
| | | | | | | | | This is the first of a few patches to reduce the dupliation of encoding information. The return instruction is a normal BR in which one of the registers is fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191364 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add instruction-shortening passRichard Sandiford2013-09-25
| | | | | | | | | | | | | | | | | | | | | | When loading immediates into a GR32, the port prefered LHI, followed by LLILH or LLILL, followed by IILF. LHI and IILF are natural 32-bit operations, but LLILH and LLILL also clear the upper 32 bits of the register. This was represented as taking a 32-bit subreg of a 64-bit assignment. Using subregs for something as simple as a move immediate was probably a bad idea. Also, I have patches to add support for the high-word facility, and we don't want something like LLILH and LLILL to stop the high word of the same GPR from being used. This patch therefore uses LHI and IILF to begin with and adds a late machine-specific pass to use LLILH and LLILL if the other half of the register is not live. The high-word patches extend this behavior to IIHF, LLIHL and LLIHH. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191363 91177308-0d34-0410-b5e6-96231b3b80d8
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