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path: root/lib/Target/X86/X86ISelLowering.cpp
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* Remove a recently redundant transform from X86ISelLowering.David Majnemer2013-05-05
| | | | | | | | | | | | | X86ISelLowering has support to treat: (icmp ne (and (xor %flags, -1), (shl 1, flag)), 0) as if it were actually: (icmp eq (and %flags, (shl 1, flag)), 0) However, r179386 has code at the InstCombine level to handle this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an odd comment.Nadav Rotem2013-05-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181136 91177308-0d34-0410-b5e6-96231b3b80d8
* 80-col fixup.Michael Liao2013-05-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180915 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid duplicating logic on frame register selecting when lowering eh_returnMichael Liao2013-05-02
| | | | | | | | No functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid duplicating logic on frame register selecting when lowering frameaddrMichael Liao2013-05-02
| | | | | | | | No functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180912 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused ShouldFoldAtomicFences flag.Tim Northover2013-04-20
| | | | | | | | I think it's almost impossible to fold atomic fences profitably under LLVM/C++11 semantics. As a result, this is now unused and just cluttering up the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179940 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
* Use 'array_lengthof' as possible to avoid magic numbersMichael Liao2013-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't ↵Benjamin Kramer2013-04-18
| | | | | | | | available. This pattern started popping up in vectorized min/max reductions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize vector select from all 0s or all 1sMichael Liao2013-04-11
| | | | | | | | | | As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance bool simplifcation in X86 to handle more casesMichael Liao2013-04-11
| | | | | | | | | | | | | | This patch is revised based on patch from Victor Umansky <victor.umansky@intel.com>. More cases are handled in X86's bool simplification, i.e. - SETCC_CARRY - value is truncated to i1 with AND As a by-product, PR5443 is also fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
* __sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not inEvan Cheng2013-04-10
| | | | | | | | | xmm0 / xmm1. rdar://13599493 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179141 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the target options specified on a function to reset the back-end.Bill Wendling2013-04-05
| | | | | | | | | During LTO, the target options on functions within the same Module may change. This would necessitate resetting some of the back-end. Do this for X86, because it's a Friday afternoon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.Benjamin Kramer2013-03-31
| | | | | | A vector sext + sitofp is a lot cheaper than 8 scalar conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the old CodePlacementOpt pass.Benjamin Kramer2013-03-29
| | | | | | It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance boolean simplification to handle 16-/64-bit RDRANDMichael Liao2013-03-28
| | | | | | | | | | | - RDRAND always clears the destination value when a random value is not available (i.e. CF == 0). This value is truncated or zero-extended as the false boolean value to be returned. Boolean simplification needs to skip this 'zext' or 'trunc' node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip moving call address loading into callseq when targets prefer register ↵Michael Liao2013-03-28
| | | | | | | | | | | | | | | | | | | | indirect call. To enable a load of a call address to be folded with that call, this load is moved from outside of callseq into callseq. Such a moving adds a non-glued node (that load) into a glued sequence. This non-glue load is only removed when DAG selection folds them into a memory form call instruction. When such instruction selection is disabled, it breaks DAG schedule. To prevent that, such moving is disabled when target favors register indirect call. Previous workaround disabling CALL32m/CALL64m insn selection is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
* Make Win32 put the SRet address into EAX, fixes PR15556Timur Iskhodzhanov2013-03-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178291 91177308-0d34-0410-b5e6-96231b3b80d8
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-27
| | | | | | | | | | | | | | | indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo (common to both X86 and PPC)Hal Finkel2013-03-27
| | | | | | Thanks to Bill Schmidt for pointing this out during code review! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178170 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XTEST codegen supportMichael Liao2013-03-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
* Revise alignment checking/calculation on 256-bit unaligned memory accessMichael Liao2013-03-25
| | | | | | | | | | | - It's still considered aligned when the specified alignment is larger than the natural alignment; - The new alignment for the high 128-bit vector should be min(16, alignment) as the pointer is advanced by 16, a power-of-2 offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177947 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15296Michael Liao2013-03-20
| | | | | | | | | - Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark all variable shifts needing customizingMichael Liao2013-03-20
| | | | | | | | | - Prepare moving logic from DAG combining into DAG lowering. There's no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177477 91177308-0d34-0410-b5e6-96231b3b80d8
* Move scalar immediate shift lowering into a dedicated funcMichael Liao2013-03-20
| | | | | | | | - no functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177476 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.Nadav Rotem2013-03-19
| | | | | | | | Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177421 91177308-0d34-0410-b5e6-96231b3b80d8
* TLS support for MinGW targets.Anton Korobeynikov2013-03-18
| | | | | | | | | MinGW is almost completely compatible to MSVC, with the exception of the _tls_array global not being available. Patch by David Nadlinger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177257 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15309Michael Liao2013-03-14
| | | | | | | | - Fix the typo on type checking git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Use correct value type for checking legality of BR_CC v3Tom Stellard2013-03-08
| | | | | | | | | | | | | LegalizeDAG.cpp uses the value of the comparison operands when checking the legality of BR_CC, so DAGCombiner should do the same. v2: - Expand more BR_CC value types for NVPTX v3: - Expand correct BR_CC value types for Hexagon, Mips, and XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.Benjamin Kramer2013-03-07
| | | | | | | | | | That can usually be lowered efficiently and is common in sandybridge code. It would be nice to do this in DAGCombiner but we can't insert arbitrary BUILD_VECTORs this late. Fixes PR15462. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176634 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two remaining issue after fixing PR15355 when CMOV is not availableMichael Liao2013-03-07
| | | | | | | | | | | | | - Phi nodes should be replaced/updated after lowering CMOV into branch because 'mainMBB' updating operand in Phi node is changed. - Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as we will reuse the EFLAGS generated before the 1st lowered CMOV, which won't clobber EFLAGS. However, we need explicitly specify that. - '-attr=-cmov' test case are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176598 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15355Michael Liao2013-03-06
| | | | | | | | | | | | | | | - Clear 'mayStore' flag when loading from the atomic variable before the spin loop - Clear kill flag from one use to multiple use in registers forming the address to that atomic variable - don't use a physical register as live-in register in BB (neither entry nor landing pad.) by copying it into virtual register (patch by Cameron Zwarich) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176538 91177308-0d34-0410-b5e6-96231b3b80d8
* Bypass Slow DividesPreston Gurd2013-03-04
| | | | | | | | | | | | | | | | * Only apply divide bypass optimization when not optimizing for size. * Fixed bug caused by constant for 0 value of type Int32, used dividend type to generate the constant instead. * For atom x86-64 apply the divide bypass to use 16-bit divides instead of 64-bit divides when operand values are small enough. * Added lit tests for 64-bit divide bypass. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10475Michael Liao2013-03-01
| | | | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
* Refine fix to PR10499, no functionality changeMichael Liao2013-02-25
| | | | | | | | - Put expensive checking after simple one git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176060 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10499Michael Liao2013-02-25
| | | | | | | | | - Check whether SSE is available before lowering all 1s vector building with PCMPEQD, which is only available from SSE2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176058 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r169638 because it broke Mesa llvmpipe tests.Nadav Rotem2013-02-24
| | | | | | | | Fix PR15239. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175985 91177308-0d34-0410-b5e6-96231b3b80d8
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-20
| | | | | | | | | | | http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
* I optimized the following patterns:Elena Demikhovsky2013-02-20
| | | | | | | | | | | | | | | | | sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix capitalization in comment to match function name.Craig Topper2013-02-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175497 91177308-0d34-0410-b5e6-96231b3b80d8
* Use array_pod_sort instead of std::sort.Jakub Staszak2013-02-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175472 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanups. No functionality change.Jakub Staszak2013-02-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175359 91177308-0d34-0410-b5e6-96231b3b80d8
* 80-colNadav Rotem2013-02-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175189 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-14
| | | | | | Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't build tail calls to functions with three inreg arguments on x86-32 PIC.Nick Lewycky2013-02-13
| | | | | | | Fixes PR15250! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175092 91177308-0d34-0410-b5e6-96231b3b80d8
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-13
| | | | | | assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MRI liveouts to X86 return instructions.Jakob Stoklund Olesen2013-02-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174402 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Open up some opportunities for constant folding by postponing shift ↵Benjamin Kramer2013-02-04
| | | | | | | | lowering. Fixes PR15141. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174327 91177308-0d34-0410-b5e6-96231b3b80d8
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