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* AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq.Elena Demikhovsky2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198745 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without)Elena Demikhovsky2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198593 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: changed property name from "neverHasSideEffects=1" to ↵Elena Demikhovsky2014-01-05
| | | | | | | | | "hasSideEffects=0", added this property to VMOVSS/VMOVSD; Optimized a truncate pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198562 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more intrinsics for convert and min/max.Elena Demikhovsky2014-01-05
| | | | | | | Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198557 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark x86 _alt instructions as AsmParserOnly so they will be omitted from ↵Craig Topper2014-01-05
| | | | | | disassembler without string matches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new x86 specific instruction flag to force some isCodeGenOnly ↵Craig Topper2014-01-05
| | | | | | instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler ↵Craig Topper2014-01-02
| | | | | | table builder doesn't need to string match them to exclude them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-01
| | | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Result type of scalar SETCC is MVT::i1 for AVX-512.Elena Demikhovsky2013-12-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198008 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed some patterns for MVT::i1Elena Demikhovsky2013-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197981 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX512: SETCC returns i1 for AVX-512 and i8 for all othersElena Demikhovsky2013-12-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197876 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey ↵Elena Demikhovsky2013-12-17
| | | | | | | | | Bader). Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197482 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added legal type MVT::i1 and VK1 register for it.Elena Demikhovsky2013-12-16
| | | | | | | | | | Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Removed "z" suffix from AVX-512 instructions, since it is ↵Elena Demikhovsky2013-12-11
| | | | | | | | | | incompatible with GCC. I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: changed intrinsics for mask operationsElena Demikhovsky2013-12-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196918 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin formElena Demikhovsky2013-12-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196914 91177308-0d34-0410-b5e6-96231b3b80d8
* Update AVX512 vector blend intrinsic names.Cameron McInally2013-12-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196581 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX512 patterns for v16i32 broadcast and v2i64 zero extend load.Cameron McInally2013-12-05
| | | | | | | Patch by Aleksey Bader. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196435 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembly syntax for AVX512 vector blend instructions.Cameron McInally2013-12-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196393 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Handled extractelement from mask vector;Elena Demikhovsky2013-11-14
| | | | | | | Added VMOSHDUP/VMOVSLDUP shuffle instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AVX512 masked vector blend intrinsics.Cameron McInally2013-11-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194006 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-03
| | | | | | | added EVEX_KZ to tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX512 unmasked integer broadcast intrinsics and support.Cameron McInally2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193748 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: PMIN/PMAX intrinsics and patternsElena Demikhovsky2013-10-27
| | | | | | | Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193497 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86][AVX512] Add patterns that match the AVX512 floating point register ↵Quentin Colombet2013-10-25
| | | | | | | | | vbroadcast intrinsics. Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193422 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86][AVX512] Add patterns that match the AVX512 floating point vbroadcast ↵Quentin Colombet2013-10-25
| | | | | | | | | intrinsics. Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193421 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsicsElena Demikhovsky2013-10-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193312 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: aligned / unaligned load and store for 512-bit integer vectors.Elena Demikhovsky2013-10-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193156 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 vector element shift-by-immediate instructions take i8 immediates. MakeLang Hames2013-10-21
| | | | | | | | | | | | | | | | the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes <rdar://problem/14968098> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more filters from the disassembler. Mark some AVX512 instructions as ↵Craig Topper2013-10-12
| | | | | | CodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing HasAVX512 predicate.Andrew Trick2013-10-09
| | | | | | | This was only working because AVX had cheaper rules in all cases. I'm sure there are other places in this file where predicates are missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192276 91177308-0d34-0410-b5e6-96231b3b80d8
* Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB ↵Craig Topper2013-10-09
| | | | | | prefix and keeps the mnemonic from starting with an extra 'v' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192272 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-06
| | | | | | | Fixed load folding in VPERM2I instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed shuffle loweringElena Demikhovsky2013-10-06
| | | | | | | in case of BLEND and added VSHUFPS patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Fixed encoding of VMOVQ instruction.Elena Demikhovsky2013-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191889 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 targetElena Demikhovsky2013-10-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added TB prefix to all instructions without prefixes,Elena Demikhovsky2013-10-02
| | | | | | | otherwise encoding fails after the last change in X86MCCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added X86vzmovl patternsElena Demikhovsky2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
* Put HasAVX512 predicate on some patterns to properly disable them when ↵Craig Topper2013-09-27
| | | | | | AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191490 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Converted to Unix styleElena Demikhovsky2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190851 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-13
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-12
| | | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added GATHER and SCATTER instructions.Elena Demikhovsky2013-09-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189729 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added extend and truncate instructions.Elena Demikhovsky2013-08-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABSElena Demikhovsky2013-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189472 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added conversion instructions.Elena Demikhovsky2013-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added FMA instructions.Elena Demikhovsky2013-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189326 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added shuffle instructions - Elena Demikhovsky2013-08-26
| | | | | | | | VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN single and double forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectorsElena Demikhovsky2013-08-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
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