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path: root/lib/Target/X86/X86InstrArithmetic.td
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* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-13
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-31
| | | | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix IMULX machine model. Multiple def operands require multiple SchedWrites.Andrew Trick2013-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184566 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct the def registers for the 8bit x86 divide instructions toEric Christopher2013-06-11
| | | | | | | match the comments and what the instruction actually does. Noticed on inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183809 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix Defs/Uses for insts that imp-def/imp-use both an A-register and EFLAGS.Ahmed Bougacha2013-05-29
| | | | | | | | | | | | | | | This corrects a problem where x86 instructions that implicitly define/use both an A-register (RAX, EAX, ..) and EFLAGS were declared as only defining/using EFLAGS, because the outer "let Defs/Uses = [EFLAGS]" in the various multiclasses overrides the "let Defs/Uses = [areg]" in BinOpAI. The instructions deriving from BinOpAI were moved out of the "let Defs", and a BinOpAI_FF class was created, for instructions that implicitly define and use EFLAGS and the A-register (SBC, ADC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182883 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-26
| | | | | | | | | | Now all x86 instructions that have itinerary classes also have SchedRW lists. This is required before the new scheduling models can be used. There are still unannotated instructions remaining, but they don't have itinerary classes either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178051 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate remaining IIC_BIN_* instructions.Jakob Stoklund Olesen2013-03-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate X86 arithmetic instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-18
| | | | | | | | | This new-style scheduling information is going to replace the instruction iteneraries. This also serves as a test case for Andy's fix in r177317. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177323 91177308-0d34-0410-b5e6-96231b3b80d8
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-14
| | | | | | -feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
* Two changes relevant to LEA and x32:David Sehr2013-02-01
| | | | | | | | | | | | 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174208 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove # from the beginning and end of def names.Craig Topper2013-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171696 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r171461 which was incorrectly reverted. Mark DIV/IDIV instructions ↵Craig Topper2013-01-05
| | | | | | hasSideEffects=1 because they can trap when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171608 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Mark DIV/IDIV instructions hasSideEffects=1 because they can trap ↵Michael Gottesman2013-01-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when dividing by 0. This is needed to keep early if conversion from moving them across basic blocks." This reverts commit r171461 since it breaks the following tests: Clang :: Analysis/outofbound-notwork.c Clang :: Analysis/string-fail.c Clang :: CXX/basic/basic.lookup/basic.lookup.qual/p6-0x.cpp Clang :: CXX/basic/basic.lookup/basic.lookup.unqual/p15.cpp Clang :: CXX/dcl.dcl/dcl.spec/dcl.fct.spec/p4.cpp Clang :: CXX/dcl.dcl/dcl.spec/dcl.stc/p10.cpp Clang :: CXX/temp/temp.param/p14.cpp Clang :: CXX/temp/temp.res/temp.dep.res/temp.point/p1.cpp Clang :: CodeGen/2009-02-13-zerosize-union-field-ppc.c Clang :: CodeGen/blocks-2.c Clang :: CodeGen/libcalls-d.c Clang :: CodeGen/libcalls-ld.c Clang :: CodeGenCXX/conversion-function.cpp Clang :: CodeGenCXX/debug-info-limit-type.cpp Clang :: CodeGenCXX/inheriting-constructor.cpp Clang :: FixIt/fixit-errors.c Clang :: FixIt/fixit-pmem.cpp Clang :: Modules/namespaces.cpp Clang :: PCH/changed-files.c Clang :: PCH/pr4489.c Clang :: PCH/source-manager-stack.c Clang :: Parser/cxx-ambig-decl-expr-xfail.cpp Clang :: SemaCXX/switch-implicit-fallthrough-cxx98.cpp Clang :: SemaTemplate/instantiate-function-1.mm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171466 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark DIV/IDIV instructions hasSideEffects=1 because they can trap when ↵Craig Topper2013-01-03
| | | | | | dividing by 0. This is needed to keep early if conversion from moving them across basic blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171461 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the divide instructions as hasSideEffects=0.Craig Topper2012-12-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171136 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hasSideEffects=0 to CMP*rr_REV.Craig Topper2012-12-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the AL/AX/EAX forms of the basic arithmetic operations has never having ↵Craig Topper2012-12-26
| | | | | | side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171121 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark all the _REV instructions as not having side effects. They aren't ↵Craig Topper2012-12-26
| | | | | | really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also ↵Craig Topper2012-12-17
| | | | | | add ANDN to isDefConvertible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170305 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: enable CSE between CMP and SUBManman Ren2012-08-08
| | | | | | | | | | | | | | | We perform the following: 1> Use SUB instead of CMP for i8,i16,i32 and i64 in ISel lowering. 2> Modify MachineCSE to correctly handle implicit defs. 3> Convert SUB back to CMP if possible at peephole. Removed pattern matching of (a>b) ? (a-b):0 and like, since they are handled by peephole now. rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161462 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: remove redundant cmp against zero.Manman Ren2012-07-18
| | | | | | | | | | Updated OptimizeCompare in peephole to remove redundant cmp against zero. We only remove Compare if CF and OF are not used. rdar://11855129 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160454 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: peephole optimization to remove cmp instructionManman Ren2012-07-06
| | | | | | | | | | For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r157831Manman Ren2012-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157896 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: peephole optimization to remove cmp instructionManman Ren2012-06-01
| | | | | | | | | | | | | | | | This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds X86 instruction itineraries, which were missed by thePreston Gurd2012-04-09
| | | | | | | | original patch to add itineraries, to X86InstrArithmetc.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154320 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-01
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 MULX instruction for disassembler.Craig Topper2011-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142738 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ↵Craig Topper2011-10-22
| | | | | | multiply instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142737 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.Jakob Stoklund Olesen2011-10-08
| | | | | | | | | | | | | In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot target all GR8 registers, only those in GR8_NOREX. TO enforce this, we ensure that all instructions using the EXTRACT_SUBREG are GR8_NOREX constrained. This fixes PR11088. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-02
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-11
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-15
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (whichChris Lattner2010-12-20
| | | | | | | | | | | | | | | | their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122213 91177308-0d34-0410-b5e6-96231b3b80d8
* it turns out that when ".with.overflow" intrinsics were added to the X86Chris Lattner2010-12-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | backend that they were all implemented except umul. This one fell back to the default implementation that did a hi/lo multiply and compared the top. Fix this to check the overflow flag that the 'mul' instruction sets, so we can avoid an explicit test. Now we compile: void *func(long count) { return new int[count]; } into: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] seto %cl ## encoding: [0x0f,0x90,0xc1] testb %cl, %cl ## encoding: [0x84,0xc9] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL instead of: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL Other than the silly seto+test, this is using the o bit directly, so it's going in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120935 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a subtle bug I introduced in my refactoring, where we stopped preferringChris Lattner2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the i8 versions of instructions in some cases. In test6, we started generating: cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00] ## <MCInst #478 CMP64mi32 ## <MCOperand Reg:114> ## <MCOperand Imm:1> ## <MCOperand Reg:0> ## <MCOperand Imm:-8> ## <MCOperand Reg:0> ## <MCOperand Imm:0>> instead of: cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00] ## <MCInst #479 CMP64mi8 ## <MCOperand Reg:114> ## <MCOperand Imm:1> ## <MCOperand Reg:0> ## <MCOperand Imm:-8> ## <MCOperand Reg:0> ## <MCOperand Imm:0>> Fix this and add some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116053 91177308-0d34-0410-b5e6-96231b3b80d8
* convert test to use the existing classes that the multipatternsChris Lattner2010-10-07
| | | | | | | | | | use. Since TEST is completely different than all other binops, don't define a multipattern for it. This completes factorization of binops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115982 91177308-0d34-0410-b5e6-96231b3b80d8
* convert cmp to use a multipatternChris Lattner2010-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115978 91177308-0d34-0410-b5e6-96231b3b80d8
* reduce redundancy between pattern copies.Chris Lattner2010-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115968 91177308-0d34-0410-b5e6-96231b3b80d8
* the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.Chris Lattner2010-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115967 91177308-0d34-0410-b5e6-96231b3b80d8
* convert adc/sbb to a multipattern. Because the adde/sube nodes Chris Lattner2010-10-07
| | | | | | | | | | | | are not defined as returning EFLAGS (like add_flag and friends), the entire multipattern and several of the subclasses need to be cloned. This could be handled through better instantiation support in tblgen, but it isn't meta enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115964 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,Chris Lattner2010-10-07
| | | | | | | allowing us to convert ADD over. deletes 160 lines of .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115897 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few issues in ArithBinOpEFLAGS that made it specific to and.Chris Lattner2010-10-07
| | | | | | | | | | Start using ArithBinOpEFLAGS for OR, XOR, and SUB. This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all defined exactly the same way instead of being close relatives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115896 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert 'and' to single instance of a multipatternChris Lattner2010-10-07
| | | | | | | | | | | | | which instantiates the 34 versions of and all in one swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not be required, but tblgen's feeble brain explodes when I use Or4<BaseOpc>.V in the multipattern. No change in the generated .inc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115893 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new BinOpAI class to represent the immediate form that directly acts ↵Chris Lattner2010-10-07
| | | | | | | | | | | on EAX. This does change the generated .inc files to include the implicit use/def of eax. Since these instructions are only generated by the assembler and disassembler it doesn't actually matter though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
* add a bunch of classes for other common patterns.Chris Lattner2010-10-07
| | | | | | | As usual, no change in generated .inc files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115882 91177308-0d34-0410-b5e6-96231b3b80d8
* Define a new BinOpRI8 class and use it to define the imm8 versions of and.Chris Lattner2010-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115880 91177308-0d34-0410-b5e6-96231b3b80d8
* add the pattern operator to match to X86TypeInfo, use this to Chris Lattner2010-10-07
| | | | | | | convert AND64ri32 to use BinOpRI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115878 91177308-0d34-0410-b5e6-96231b3b80d8
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