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path: root/lib/Target/X86/X86InstrCMovSetCC.td
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* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-10
| | | | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201065 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r201059 and r201060.Bob Wilson2014-02-10
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201064 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-10
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201059 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-02
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-08
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198752 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate X86InstrCMovSetCC.td with SchedRW lists.Jakob Stoklund Olesen2013-03-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177459 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove # from the beginning and end of def names.Craig Topper2013-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171696 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-01
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Move cmov pseudo instructions to InstrCompiler,Chris Lattner2010-10-05
| | | | | | | | | | | | | convert all the rest of the cmovs to the multiclass, with good results: X86InstrCMovSetCC.td | 598 +-------------------------------------------------- X86InstrCompiler.td | 61 +++++ 2 files changed, 77 insertions(+), 582 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115707 91177308-0d34-0410-b5e6-96231b3b80d8
* Use #NAME# to have the CMOV multiclass define things with the same names as ↵Chris Lattner2010-10-05
| | | | | | | | | before (e.g. CMOVBE16rr instead of CMOVBErr16). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115705 91177308-0d34-0410-b5e6-96231b3b80d8
* switch CMOVBE to the multipattern:Chris Lattner2010-10-05
| | | | | | | | | 21 insertions(+), 53 deletions(-) Moar change coming before I switch the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115697 91177308-0d34-0410-b5e6-96231b3b80d8
* add a multiclass for cmov's, but don't start using it yet.Chris Lattner2010-10-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115692 91177308-0d34-0410-b5e6-96231b3b80d8
* use a multipattern to define setcc instructions:Chris Lattner2010-10-05
| | | | | | | | | | X86InstrCMovSetCC.td | 200 ++++++--------------------------------------------- 1 file changed, 27 insertions(+), 173 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115689 91177308-0d34-0410-b5e6-96231b3b80d8
* move SETB pseudos into the same place in InstrCompiler.tdChris Lattner2010-10-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
* split conditional moves and setcc's out to their own file.Chris Lattner2010-10-05
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115601 91177308-0d34-0410-b5e6-96231b3b80d8
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