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path: root/lib/Target/X86/X86InstrFPStack.td
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* Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-26
| | | | | | | This only covers the instructions that were given itinerary classes for the Atom model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178050 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-02
| | | | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Don't emit conditional floating point moves on when targeting ↵Benjamin Kramer2012-04-27
| | | | | | | | | | | | | | | | pre-pentiumpro architectures. * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
* some comment fix for X86 and ARMJia Liu2012-02-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper2012-01-10
| | | | | | predicates. Another commit will remove orAVX functions from X86SubTarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable FISTTP* instructions when AVX is enabled.Craig Topper2012-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147758 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel style asm variant does not need '%' prefix.Devang Patel2012-01-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147453 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-28
| | | | | | | | | | | | | | | | | | | | Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134018 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.Reid Kleckner2011-02-12
| | | | | | | | | These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use 64-bit pointer values instead of 32-bit pointer values in the memory map they dump and restore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
* Move X86InstrFPStack.td over to PseudoI as well.Eric Christopher2010-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120470 91177308-0d34-0410-b5e6-96231b3b80d8
* go to great lengths to work around a GAS bug my previous patchChris Lattner2010-11-06
| | | | | | | | | | | | | | | | | exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-06
| | | | | | | | | listed in its asm string, for consistency with the other similar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting r117031 to cleanup valgrind errors.Andrew Trick2010-10-22
| | | | | | | | It doesn't look like anything is wrong with the checkin, but the new test cases expose a mem bug in AsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117087 91177308-0d34-0410-b5e6-96231b3b80d8
* More tweaks to X86 instructions to allow the 'w' suffix in places it makesKevin Enderby2010-10-21
| | | | | | | | | | sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Also added the missing flex (without the wait prefix) and ud2a as an alias to ud2 (still to add ud2b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117031 91177308-0d34-0410-b5e6-96231b3b80d8
* allow !strconcat to take more than two operands to eliminateChris Lattner2010-10-05
| | | | | | | | | !strconcat(!strconcat(!strconcat(!strconcat Simplify some x86 td files to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115719 91177308-0d34-0410-b5e6-96231b3b80d8
* refactor .td files a bit, moving system instructions out to X86InstrSystem.tdChris Lattner2010-10-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115591 91177308-0d34-0410-b5e6-96231b3b80d8
* convert the last 4 X86ISD nodes that should have memoperands to have them.Chris Lattner2010-09-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114523 91177308-0d34-0410-b5e6-96231b3b80d8
* give FP_TO_INT16_IN_MEM and friends a memoperand. They are onlyChris Lattner2010-09-22
| | | | | | | used with stack slots, but hey, lets be safe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114521 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment typos.Bob Wilson2010-08-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112202 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKillJakob Stoklund Olesen2010-07-16
| | | | | | | | | pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108536 91177308-0d34-0410-b5e6-96231b3b80d8
* Use target independent COPY instructions for the fake fextend and froundJakob Stoklund Olesen2010-07-11
| | | | | | operations in x87 code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108098 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isTwoAddress from here too.Eric Christopher2010-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106358 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed llvm-mc to use the same suffixes with floating point compareKevin Enderby2010-05-03
| | | | | | | | instructions as the Mac OS X darwin assembler. Some of which like 'fcoml' assembled to different opcodes. While some of the suffixes were just different. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102958 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that tblgen can handle matching implicit defs of instructionsChris Lattner2010-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking two inputs (which have to be the same type) and *returning an i32*. This is how the SDNodes get made in the graph, but we weren't able to model it this way due to deficiencies in the pattern language. Now we can change things like this: def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, - [(X86cmp RFP80:$lhs, RFP80:$rhs), - (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i) + [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; and fix terrible crimes like this: -def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)), +def : Pat<(X86cmp GR8:$src1, 0), (TEST8rr GR8:$src1, GR8:$src1)>; This relies on matching the result of TEST8rr (which is EFLAGS, which is an implicit def) to the result of X86cmp, an i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for pentium class CPUs which do not have cmov,Chris Lattner2010-03-14
| | | | | | | PR4841. Patch by Craig Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98496 91177308-0d34-0410-b5e6-96231b3b80d8
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a case where we'd mis-encode fisttp because of an incorrect (andChris Lattner2010-02-05
| | | | | | | redundant with a correct one) pattern that was added for the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95446 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-29
| | | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed a few instructions that were alreadySean Callanan2009-09-16
| | | | | | | covered by other definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81992 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a variety of floating-point and SSE instructions.Sean Callanan2009-09-16
| | | | | | | | | | | | | All of these do not have patterns (they're for the disassembler). Many of the floating-point instructions will probably be rolled into definitions that have patterns, and may eventually be superseded by mdefs. So I put them together and left a comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81979 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement FpSET_ST1_*.Evan Cheng2009-02-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64186 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ## for comment delimiter on darwin x86-32, soDale Johannesen2008-03-25
| | | | | | | | | | llvm's output .s files will go through gcc -std=c99 without triggering preprocesser errors. Approach suggested by Daveed Vandevoorde. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48808 91177308-0d34-0410-b5e6-96231b3b80d8
* remove Evan's "ugly hack" that sorta attempted to get Chris Lattner2008-03-21
| | | | | | | | x86-64 return conventions correct, but was never enabled. We can now do the "right thing" with multiple return values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48635 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for calls that return two FP values inChris Lattner2008-03-21
| | | | | | | ST(0)/ST(1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48634 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to Chris Lattner2008-03-10
| | | | | | | | copyfromreg/copytoreg instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
* rename FP_SETRESULT -> FP_SET_ST0Chris Lattner2008-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48094 91177308-0d34-0410-b5e6-96231b3b80d8
* rename FpGETRESULT32 -> FpGET_ST0_32 etc. Add support forChris Lattner2008-03-09
| | | | | | | | isel'ing value preserving FP roundings from one fp stack reg to another into a noop, instead of stack traffic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48093 91177308-0d34-0410-b5e6-96231b3b80d8
* Work in progress. This patch *fixes* x86-64 calls which are modelled as ↵Evan Cheng2008-01-29
| | | | | | | | | StructRet but really should be return in registers, e.g. _Complex long double, some 128-bit aggregates. This is a short term solution that is necessary only because llvm, for now, cannot model i128 nor call's with multiple results. Status: This only works for direct calls, and only the caller side is done. Disabled for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46527 91177308-0d34-0410-b5e6-96231b3b80d8
* more flags set rightChris Lattner2008-01-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45860 91177308-0d34-0410-b5e6-96231b3b80d8
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-10
| | | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
* remove explicit sets of 'neverHasSideEffects' that can now be Chris Lattner2008-01-10
| | | | | | | inferred from the instr patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45824 91177308-0d34-0410-b5e6-96231b3b80d8
* get def use info more correct.Chris Lattner2008-01-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. IBill Wendling2007-12-17
| | | | | | | | | | based what flag to set on whether it was already marked as "isRematerializable". If there was a further check to determine if it's "really" rematerializable, then I marked it as "mayHaveSideEffects" and created a check in the X86 back-end similar to the remat one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45132 91177308-0d34-0410-b5e6-96231b3b80d8
* LD_Fp64m should have "isRematerializable" set.Bill Wendling2007-12-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45128 91177308-0d34-0410-b5e6-96231b3b80d8
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