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* AVX-512: aligned / unaligned load and store for 512-bit integer vectors.Elena Demikhovsky2013-10-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193156 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-12
| | | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added extend and truncate instructions.Elena Demikhovsky2013-08-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure x86 instructions using ssmem/sdmem operand types are only able to ↵Craig Topper2013-08-26
| | | | | | parse memory operands of the proper size in Intel syntax. Primarily affects some of sse cvt instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189206 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added SHIFT instructions.Elena Demikhovsky2013-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added arithmetic and logical operations.Elena Demikhovsky2013-08-19
| | | | | | | | ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188673 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.Elena Demikhovsky2013-08-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use v16i32 for load pattern matching. All 512-bit loads are cated to ↵Craig Topper2013-08-16
| | | | | | v8i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188534 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added CMP and BLEND instructions.Elena Demikhovsky2013-08-13
| | | | | | | Lowering for SETCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.Elena Demikhovsky2013-08-11
| | | | | | | Added a test for shuffles using VPERM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: Added BROADCAST instructionsElena Demikhovsky2013-08-07
| | | | | | | with lowering logic and a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.Elena Demikhovsky2013-08-05
| | | | | | | Added intrinsics and tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Turn fp selects into mask operations.Benjamin Kramer2013-08-04
| | | | | | | | | | | | | | | | | | | | | | | double test(double a, double b, double c, double d) { return a<b ? c : d; } before: _test: ucomisd %xmm0, %xmm1 ja LBB0_2 movaps %xmm3, %xmm2 LBB0_2: movaps %xmm2, %xmm0 after: _test: cmpltsd %xmm1, %xmm0 andpd %xmm0, %xmm2 andnpd %xmm3, %xmm0 orpd %xmm2, %xmm0 Small speedup on Benchmarks/SmallPT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-31
| | | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper2013-01-28
| | | | | | instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Match the SSE/AVX min/max vector ops using a custom node instead of ↵Benjamin Kramer2012-12-21
| | | | | | | | intrinsics This is very mechanical, no functionality change. Preparation for PR14667. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Add a couple of target-specific dag combines that turn VSELECTS into ↵Benjamin Kramer2012-12-15
| | | | | | | | | | | psubus if possible. We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases if y is a constant. DAGCombiner canonicalizes those so we first have to undo the canonicalization for those cases. The pattern occurs in gzip when the loop vectorizer is enabled. Part of PR14613. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170273 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplified BLEND pattern matching for shuffles.Elena Demikhovsky2012-12-05
| | | | | | Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169366 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1Michael Liao2012-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for FP_ROUND from v2f64 to v2f32Michael Liao2012-10-10
| | | | | | | | | | | | - Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance PR11334 fix to support extload from v2f32/v4f32Michael Liao2012-09-10
| | | | | | | | - Fix an remaining issue of PR11674 as well git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163528 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert FMA4 patterns to use target specific nodes instead of intrinsics to ↵Craig Topper2012-08-29
| | | | | | align with FMA3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162829 91177308-0d34-0410-b5e6-96231b3b80d8
* When unsafe math is used, we can use commutative FMAX and FMIN. In some casesNadav Rotem2012-08-19
| | | | | | | | | | | | | | | | | | | | | | this allows for better code generation. Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and FMINC, which are commutative. For example: movaps %xmm0, %xmm1 movsd LC(%rip), %xmm0 minsd %xmm1, %xmm0 becomes: minsd LC(%rip), %xmm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162187 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR11334Michael Liao2012-08-14
| | | | | | | | | | | | | | - FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement proper handling for pcmpistri/pcmpestri intrinsics. Requires ↵Craig Topper2012-08-06
| | | | | | custom handling in DAGISelToDAG due to limitations in TableGen's implicit def handling. Fixes PR11305. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161318 91177308-0d34-0410-b5e6-96231b3b80d8
* Added FMA functionality to X86 target.Elena Demikhovsky2012-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tabs.Bill Wendling2012-07-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160477 91177308-0d34-0410-b5e6-96231b3b80d8
* Use XOP vpcom intrinsics in patterns instead of a target specific SDNode ↵Craig Topper2012-06-09
| | | | | | type. Remove the custom lowering code that selected the SDNode type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158279 91177308-0d34-0410-b5e6-96231b3b80d8
* ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2Elena Demikhovsky2012-04-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
* Change type profile for vpermv back to using operand type for the mask ↵Craig Topper2012-04-16
| | | | | | argument to match intrinsic behavior. Add a bitcast to the lowering code to convert mask from v8i32 to v8f32 for vpermps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154798 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge vpermps/vpermd and vpermpd/vpermq SD nodes.Craig Topper2012-04-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154782 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SDTypeProfile for vpermps. The mask operand should be v8i32.Craig Topper2012-04-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154781 91177308-0d34-0410-b5e6-96231b3b80d8
* Added VPERM optimization for AVX2 shufflesElena Demikhovsky2012-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply 154396 after fixing a test.Nadav Rotem2012-04-11
| | | | | | | | | | | Original message: Modify the code that lowers shuffles to blends from using blendvXX to vblendXX. blendV uses a register for the selection while Vblend uses an immediate. On sandybridge they still have the same latency and execute on the same execution ports. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154483 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert this patch to see if it brings the buildbots back.Eric Christopher2012-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154425 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.Nadav Rotem2012-04-10
| | | | | | | | | blendv uses a register for the selection while vblend uses an immediate. On sandybridge they still have the same latency and execute on the same execution ports. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a regression from r147481.Chad Rosier2012-03-09
| | | | | | | | | | | | | | Original commit message from r147481: DAGCombine for transforming 128->256 casts into a vmovaps, rather then a vxorps + vinsertf128 pair if the original vector came from a load. Fix: Unaligned loads need to generate a vmovups. rdar://10974078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152366 91177308-0d34-0410-b5e6-96231b3b80d8
* some comment fix for X86 and ARMJia Liu2012-02-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the last of the old vector_shuffle patterns from X86 isel.Craig Topper2012-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150795 91177308-0d34-0410-b5e6-96231b3b80d8
* Move old movl vector_shuffle patterns. Not needed anymore since ↵Craig Topper2012-02-14
| | | | | | vector_shuffles shouldn't reach isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150462 91177308-0d34-0410-b5e6-96231b3b80d8
* Still more vector_shuffle pattern removal.Craig Topper2012-02-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150365 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r150328. Previous test failures should be fixed by r150360.Craig Topper2012-02-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150362 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r150328, "Remove more vector_shuffle patterns."NAKAMURA Takumi2012-02-13
| | | | | | It caused 3 failures on pre-penryn and non-x86(generic) hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150357 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more vector_shuffle patterns.Craig Topper2012-02-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150328 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more vector_shuffle patterns.Craig Topper2012-02-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150321 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some patterns for matching vector_shuffle instructions since ↵Craig Topper2012-02-11
| | | | | | vector_shuffles should be custom lowered before isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150299 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target specific node for PMULUDQ. Change patterns to use it and custom ↵Craig Topper2012-02-05
| | | | | | lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky2012-02-02
| | | | | | | | | Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic ↵Craig Topper2012-01-30
| | | | | | patterns with custom lowering to a target specific nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
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