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* This patch produces the correct addend value forJack Carter2013-01-27
| | | | | | | | | | | an R_MIPS_GPREL16 relocation. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171882 91177308-0d34-0410-b5e6-96231b3b80d8 (cherry picked from commit 4a50e53e53816076584c957741cb430899271726) Signed-off-by: Abdoulaye Walsimou Gaye <awg@embtoolkit.org>
* Merging MIPS JIT/MCJIT changeset into 3.2 release branch.Pawel Wodnicki2012-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merging r169183: RuntimeDyld: Fix up r169178. MSVC doesn't like "or". Merging r169178: Runtime dynamic linker for MCJIT should support MIPS BigEndian architecture. This small change adds support for that. It will make all MCJIT tests pass in make-check on BigEndian platforms. Patch by Petar Jovanovic. Merging r169177: Classic JIT is still being supported by MIPS, along with MCJIT. This change adds endian-awareness to MipsJITInfo and emitWordLE in MipsCodeEmitter has become emitWord now to support both endianness. Patch by Petar Jovanovic. Merging r169174: Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are dead code. Removing it. Patch by Petar Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@169296 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging MIPS GOT changeset into 3.2 release branch.Pawel Wodnicki2012-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merging r168471: Mips direct object xgot support This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter Merging r168460: [mips] Generate big GOT code. Merging r168458: [mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. Merging r168456: [mips] Add helper functions that create nodes for computing address. Merging r168455: [mips] Add command line option "-mxgot". Merging r168453: [mips] When a node which loads from a GOT is created, pass a MachinePointerInfo referring to a GOT entry. Merging r168450: [mips] Add target operand flag enums for big GOT relocations. Merging r168448: Add relocations used for mips big GOT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@169294 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in r168799 (PPC bug fix).Hal Finkel2012-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168842 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r168512: into 3.2 release branch.Pawel Wodnicki2012-11-23
| | | | | | Update call to the new syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168526 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r168001 into 3.2 release branchPawel Wodnicki2012-11-20
| | | | | | | NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable] git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168378 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in PPC internal-as fixes: r167861, r167862, r167863, r167875, r167860, ↵Hal Finkel2012-11-20
| | | | | | r167864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168351 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge in r167737: Make PPC TOC contents deterministic.Hal Finkel2012-11-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168350 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r167718 into 3.2 release branchPawel Wodnicki2012-11-19
| | | | | | | | | | | Fix PR14314 - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168336 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r167948, r168198: into the 3.2 release branchPawel Wodnicki2012-11-19
| | | | | | | | | | | | | | | | r168198 [NVPTX] Order global variables in def-use order before emiting them in the final assembly r167948 [NVPTX] Implement custom lowering of loads/stores for i1 Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168335 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r167719 into the 3.2 relase branchPawel Wodnicki2012-11-19
| | | | | | Remove unused field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168333 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add more precise PTX/SM target attributesJustin Holewinski2012-11-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some helper methods to being static functions in the implementation file.Craig Topper2012-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167696 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the isTruncFree and isZExtFree API to figure out of these operations are ↵Nadav Rotem2012-11-11
| | | | | | free. Thanks Andy! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167685 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary subtraction and addition by 1 around a couple for loops.Craig Topper2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167673 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up spacing. No functional change.Craig Topper2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167671 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed unimplemented method declaration.Craig Topper2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167670 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper ↵Craig Topper2012-11-10
| | | | | | functions static. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167669 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more functions to the target library information.Meador Inge2012-11-10
| | | | | | | | | | | In the process of migrating optimizations from the simplify-libcalls pass to the instcombine pass I noticed that a few functions are missing from the target library information. These functions need to be available for querying in the instcombine library call simplifiers. More functions will probably be added in the future as more simplifiers are migrated to instcombine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167659 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the Thumb no-return call optimization:Evan Cheng2012-11-10
| | | | | | | | | | | | | mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.Craig Topper2012-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Use ABI alignment for parameters when alignment is not specified.Justin Holewinski2012-11-09
| | | | | | Affects SM 2.0+. Fixes bug 13324. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167646 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.Anton Korobeynikov2012-11-09
| | | | | | | Based on the patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167633 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch FreeBSD/i386 back to 4byte stack alignment. This partiallyRoman Divacky2012-11-09
| | | | | | | reverts r126226. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167632 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r167620; this can be implemented using an existing CL option.Chad Rosier2012-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for -mstrict-align compiler option for ARM targets.Chad Rosier2012-11-09
| | | | | | | rdar://12340498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
* indentNadav Rotem2012-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167607 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit modified r167540.Amara Emerson2012-11-08
| | | | | | | | Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-08
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.Akira Hatanaka2012-11-07
| | | | | | | Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167548 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete MipsFunctionInfo::NextStackOffset. No functionality change intended. Akira Hatanaka2012-11-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167546 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r167540 until regression tests are updated.Amara Emerson2012-11-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167545 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve ARM build attribute emission for architectures types.Amara Emerson2012-11-07
| | | | | | | This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167540 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-07
| | | | | | | classes. For my test case the number of errors drop from 356 to 21. Part of rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167508 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code. No functionality change.Jakub Staszak2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167505 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the helper functions static. No functional change.Nadav Rotem2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167501 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering allChad Rosier2012-11-06
| | | | | | | | | | | | registers. Previously, the register we being marked as implicitly defined, but not killed. In some cases this would cause the register scavenger to spill a dead register. Also, use an empty register mask to simplify the logic and to reduce the memory footprint. rdar://12592448 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167499 91177308-0d34-0410-b5e6-96231b3b80d8
* CostModel: add another known vector trunc optimization.Nadav Rotem2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167488 91177308-0d34-0410-b5e6-96231b3b80d8
* Cost Model: add tables for some avx type-conversion hacks.Nadav Rotem2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167480 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tailing whitespacesMichael Liao2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167445 91177308-0d34-0410-b5e6-96231b3b80d8
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-06
| | | | | | | This is in preparation for adding "weak" DAG edges, but generally simplifies the design. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the getTypeLegalizationCost interface. No functionality change.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167422 91177308-0d34-0410-b5e6-96231b3b80d8
* CostModel: Add tables for the common x86 compares.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167421 91177308-0d34-0410-b5e6-96231b3b80d8
* Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167412 91177308-0d34-0410-b5e6-96231b3b80d8
* Suppress signed/unsigned comparison warning.Richard Smith2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167410 91177308-0d34-0410-b5e6-96231b3b80d8
* Cost Model: Normalize the insert/extract index when splitting typesNadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167402 91177308-0d34-0410-b5e6-96231b3b80d8
* Cost Model: teach the cost model about expanding integers.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167401 91177308-0d34-0410-b5e6-96231b3b80d8
* On PowerPC64, integer return values (as well as arguments) are supposedUlrich Weigand2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | to be extended to a full register. This is modeled in the IR by marking the return value (or argument) with a signext or zeroext attribute. However, while these attributes are respected for function arguments, they are currently ignored for function return values by the PowerPC back-end. This patch updates PPCCallingConv.td to ask for the promotion to i64, and fixes LowerReturn and LowerCallResult to implement it. The new test case verifies that both arguments and return values are properly extended when passing them; and also that the optimizers understand incoming argument and return values are in fact guaranteed by the ABI to be extended. The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll, since the test case used a "ret" instruction to create a use of an i32 value at the end of the function (to set up data flow as required for what the test is intended to test). Since there's now an implicit promotion to i64, that data flow no longer works as expected. To fix this, this patch now adds an extra "add" to ensure we have an appropriate use of the i32 value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167396 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the cost of abnormal x86 instruction lowering as a table.Nadav Rotem2012-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167395 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the PowerPC-specific inline asm Z constraint and y modifier.Hal Finkel2012-11-05
| | | | | | | | | | The Z constraint specifies an r+r memory address, and the y modifier expands to the "r, r" in the asm string. For this initial implementation, the base register is forced to r0 (which has the special meaning of 0 for r+r addressing on PowerPC) and the full address is taken in the second register. In the future, this should be improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167388 91177308-0d34-0410-b5e6-96231b3b80d8
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