| Commit message (Collapse) | Author | Age |
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r198744 | iain | 2014-01-08 05:22:54 -0500 (Wed, 08 Jan 2014) | 8 lines
[patch] Adjust behavior of FDE cross-section relocs for targets that don't support abs-differences.
Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs.
This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff". At present, this is only enabled for modern x86 OSX ports.
test changes by David Fang.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205768 91177308-0d34-0410-b5e6-96231b3b80d8
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r197574 | rafael.espindola | 2013-12-18 10:06:25 -0500 (Wed, 18 Dec 2013) | 8 lines
Fix f64 and f128 for ppc-darwin.
This patch adds -f64:32:64 to 32 bit ppc darwin since a f64 inside a
structure are only 32 bit aligned.
The patch also drop -f128:64:128 from all ppc darwin, since f128 is
128 bit aligned.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205767 91177308-0d34-0410-b5e6-96231b3b80d8
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r197572 | rafael.espindola | 2013-12-18 09:35:37 -0500 (Wed, 18 Dec 2013) | 6 lines
One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.
Thanks for Iain Sandoe for testing this with the original gcc.
Clang was already getting this right.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205766 91177308-0d34-0410-b5e6-96231b3b80d8
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r196987 | rafael.espindola | 2013-12-10 19:09:06 -0500 (Tue, 10 Dec 2013) | 2 lines
Move PPC's getDataLayoutString out of line and document it better.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205765 91177308-0d34-0410-b5e6-96231b3b80d8
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r196168 | rafael.espindola | 2013-12-02 18:04:51 -0500 (Mon, 02 Dec 2013) | 2 lines
Convert two char* that are only ever used as booleans to bool.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205764 91177308-0d34-0410-b5e6-96231b3b80d8
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r203818 | thomas.stellard | 2014-03-13 10:13:04 -0700 (Thu, 13 Mar 2014) | 7 lines
R600: LDS instructions shouldn't implicitly define OQAP
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.
This fixes a hang in the opencv MedianFilter tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204650 91177308-0d34-0410-b5e6-96231b3b80d8
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r203281 | thomas.stellard | 2014-03-07 12:12:39 -0800 (Fri, 07 Mar 2014) | 4 lines
R600/SI: Using SGPRs is illegal for instructions that read carry-out
from VCC
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204649 91177308-0d34-0410-b5e6-96231b3b80d8
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r201097 | thomas.stellard | 2014-02-10 08:58:30 -0800 (Mon, 10 Feb 2014) | 9 lines
R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are
used
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0. When M0 is uninitialized,
then we experience undefined behavior.
This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204648 91177308-0d34-0410-b5e6-96231b3b80d8
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r201096 | thomas.stellard | 2014-02-10 08:58:27 -0800 (Mon, 10 Feb 2014) | 6 lines
R600/SI: Only use S_WQM_B64 in pixel shaders
This doesn't change any functionality, since we only have two shader
types (compute and pixel) that use local memory. We're just changing
the logic to match the documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204647 91177308-0d34-0410-b5e6-96231b3b80d8
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r200830 | michel.daenzer | 2014-02-05 01:48:05 -0800 (Wed, 05 Feb 2014) | 8 lines
R600/SI: Add pattern for zero-extending i1 to i32
Fixes opencl-example if_* tests with radeonsi.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204646 91177308-0d34-0410-b5e6-96231b3b80d8
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r200776 | thomas.stellard | 2014-02-04 09:18:43 -0800 (Tue, 04 Feb 2014) | 9 lines
R600/SI: Expand i1 BR_CC
This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.
I was unable to come up with a reduced test case for this.
https://bugs.freedesktop.org/show_bug.cgi?id=72785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204645 91177308-0d34-0410-b5e6-96231b3b80d8
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r200775 | thomas.stellard | 2014-02-04 09:18:42 -0800 (Tue, 04 Feb 2014) | 5 lines
R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopies
There is no lit test for this, because it would be too big and
complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV
test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204644 91177308-0d34-0410-b5e6-96231b3b80d8
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r200743 | michel.daenzer | 2014-02-03 23:12:38 -0800 (Mon, 03 Feb 2014) | 11 lines
R600/SI: Fix fneg for 0.0
V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.
Also add a pattern for (fneg (fabs ...)).
Fixes a bunch of bit encoding piglit tests with radeonsi.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204643 91177308-0d34-0410-b5e6-96231b3b80d8
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r200283 | michel.daenzer | 2014-01-27 19:01:16 -0800 (Mon, 27 Jan 2014) | 6 lines
R600/SI: Add pattern for truncating i32 to i1
Fixes half a dozen piglit tests with radeonsi.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204642 91177308-0d34-0410-b5e6-96231b3b80d8
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r199919 | thomas.stellard | 2014-01-23 10:49:34 -0800 (Thu, 23 Jan 2014) | 10 lines
R600: Remove successive JUMP in AnalyzeBranch when AllowModify is true
This fixes a crash in the OpenCV OpenCL test suite.
There is no lit test for this, because the test would be very large
and could easily be invalidated by changes to the scheduler
or other parts of the compiler.
Patch by: Vincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204641 91177308-0d34-0410-b5e6-96231b3b80d8
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r199918 | thomas.stellard | 2014-01-23 10:49:33 -0800 (Thu, 23 Jan 2014) | 8 lines
R600: Disable the BFE pattern
This pattern uses an SDNodeXForm, which isn't being emitted for some
reason. I can get it to work by attaching the PatLeaf that has the
XForm to the argument in the output pattern, but this results in an
immediate being used in a register operand, which the backend can't
handle yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204640 91177308-0d34-0410-b5e6-96231b3b80d8
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r199917 | thomas.stellard | 2014-01-23 10:49:31 -0800 (Thu, 23 Jan 2014) | 6 lines
R600: Correctly handle vertex fetch clauses the precede ENDIFs
The control flow finalizer would sometimes use an ALU_POP_AFTER
instruction before the vetex fetch clause instead of using a POP
instruction after it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204639 91177308-0d34-0410-b5e6-96231b3b80d8
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r202336 | michel.daenzer | 2014-02-26 17:47:02 -0800 (Wed, 26 Feb 2014) | 4 lines
R600/SI: Allow SI_KILL for geometry shaders
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204638 91177308-0d34-0410-b5e6-96231b3b80d8
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r200196 | michel.daenzer | 2014-01-26 23:20:51 -0800 (Sun, 26 Jan 2014) | 4 lines
R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204637 91177308-0d34-0410-b5e6-96231b3b80d8
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r200195 | michel.daenzer | 2014-01-26 23:20:44 -0800 (Sun, 26 Jan 2014) | 4 lines
R600/SI: Add intrinsic for S_SENDMSG instruction
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204636 91177308-0d34-0410-b5e6-96231b3b80d8
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r197520 | dexonsmith | 2013-12-17 12:28:21 -0800 (Tue, 17 Dec 2013) | 7
lines
Assert that the last operand is actually EFLAGS
This is another follow-up to r197503, after a post-commit review by
Andy.
<rdar://problem/15627766>
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r197505 | dexonsmith | 2013-12-17 08:20:37 -0800 (Tue, 17 Dec 2013) | 6
lines
Setting the CPU in the new vaargs test
Trying to fix buildbots after r197503 (test passes locally).
<rdar://problem/15627766>
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r197503 | dexonsmith | 2013-12-17 07:54:45 -0800 (Tue, 17 Dec 2013) | 17
lines
Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS""
This reverts commit r197481, recommiting r197469 with an extra fix.
The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS. Mark it so, or else the scheduler might
place it in the middle of another test+branch.
This fixes a bug exposed by r192750, which changed the initial scheduler
to source-order as part of enabling the MI Scheduler for X86.
This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to
try to save %flags, and adds a test that catches the bad behavior of
r197469.
<rdar://problem/15627766>
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@202060 91177308-0d34-0410-b5e6-96231b3b80d8
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r197492 | dyatkovskiy | 2013-12-17 04:07:33 -0800 (Tue, 17 Dec 2013) | 26 lines
Fix for PR18045:
http://llvm.org/bugs/show_bug.cgi?id=18045
Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:
$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
[ID=58]
0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
0x41dcb10: i32 = undef [ID=2]
The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.
The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal.
P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197779 91177308-0d34-0410-b5e6-96231b3b80d8
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r197228 | d0k | 2013-12-13 05:40:24 -0800 (Fri, 13 Dec 2013) | 8 lines
X86: When lowering shl_parts, don't emit shift amounts larger than the bit width.
While it's safe for the X86-specific shift nodes, dag combining will
kill generic nodes. Insert an AND to make it safe, isel will nuke it
as x86's shift instructions have an implicit AND.
Fixes PR16108, which contains a contraption to hit this case in between
constant folders.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197321 91177308-0d34-0410-b5e6-96231b3b80d8
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r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line
Remove unused multiclass from PPCInstrInfo.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197131 91177308-0d34-0410-b5e6-96231b3b80d8
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r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line
Remove unused multiclass from PPCInstrInfo.td
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197130 91177308-0d34-0410-b5e6-96231b3b80d8
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r197089 | hfinkel | 2013-12-11 15:12:25 -0800 (Wed, 11 Dec 2013) | 6 lines
Fix the PPC subsumes-predicate check
For one predicate to subsume another, they must both check the same condition
register. Failure to check this prerequisite was causing miscompiles.
Fixes PR18003.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197126 91177308-0d34-0410-b5e6-96231b3b80d8
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r196806 | apazos | 2013-12-09 11:29:14 -0800 (Mon, 09 Dec 2013) | 11 lines
Fix pattern match for movi with 0D result
Patch by Jiangning Liu.
With some test case changes:
- intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll.
- New test cases to cover movi 1D scenario without using the intrinsic in
test/CodeGen/AArch64/neon-mov.ll.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196872 91177308-0d34-0410-b5e6-96231b3b80d8
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should fix the issue.
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r196210 | haoliu | 2013-12-03 06:06:55 +0000 (Tue, 03 Dec 2013) | 3 lines
[AArch64]Add missing floating point convert, round and misc intrinsics.
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196772 91177308-0d34-0410-b5e6-96231b3b80d8
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r196725 | tnorthover | 2013-12-08 15:56:50 +0000 (Sun, 08 Dec 2013) |
19 lines
ARM: fix folding of stack-adjustment (yet again).
When trying to eliminate an "sub sp, sp, #N" instruction by folding
it into an existing push/pop using dummy registers, we need to account
for the fact that this might affect precisely how "fp" gets set in the
prologue.
We were attempting this, but assuming that *whenever* we performed a
fold it would make a difference. This is false, for example, in:
push {r4, r7, lr}
add fp, sp, #4
vpush {d8}
sub sp, sp, #8
we can fold the "sub" into the "vpush", forming "vpush {d7, d8}".
However, in that case the "add fp" instruction mustn't change, which
we were getting wrong before.
Should fix PR18160.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196769 91177308-0d34-0410-b5e6-96231b3b80d8
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r196751 | venkatra | 2013-12-08 20:02:15 -0800 (Sun, 08 Dec 2013) | 3 lines
[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196766 91177308-0d34-0410-b5e6-96231b3b80d8
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r196755 | venkatra | 2013-12-08 21:13:25 -0800 (Sun, 08 Dec 2013) | 2 lines
[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196764 91177308-0d34-0410-b5e6-96231b3b80d8
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r196735 | venkatra | 2013-12-08 14:06:07 -0800 (Sun, 08 Dec 2013) | 3 lines
[SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.
This fixes PR18150.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196744 91177308-0d34-0410-b5e6-96231b3b80d8
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function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196717 91177308-0d34-0410-b5e6-96231b3b80d8
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r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines
Bug 18149: [AArch32] VSel instructions has no ARMCC field
The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code.
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r196533 | apazos | 2013-12-05 13:07:49 -0800 (Thu, 05 Dec 2013) | 3 lines
Implemented vget/vset_lane_f16 intrinsics
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r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines
For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.
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r196362 | kevinqin | 2013-12-04 00:02:34 -0800 (Wed, 04 Dec 2013) | 1 line
[AArch64 Neon] Add ACLE intrinsic vceqz_f64.
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r196360 | kevinqin | 2013-12-03 23:53:28 -0800 (Tue, 03 Dec 2013) | 1 line
[AArch64 NEON] Add missing compare intrinsics.
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r196208 | haoliu | 2013-12-02 21:58:30 -0800 (Mon, 02 Dec 2013) | 3 lines
AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions.
E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm.
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r196198 | haoliu | 2013-12-02 19:39:47 -0800 (Mon, 02 Dec 2013) | 3 lines
AArch64: Add missing scalar pair intrinsics.
E.g. "float32_t vaddv_f32(float32x2_t a)" to be matched into "faddp s0, v1.2s".
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r196192 | jiangning | 2013-12-02 17:33:52 -0800 (Mon, 02 Dec 2013) | 2 lines
Add some missing pattern matches for AArch64 Neon intrinsics like vuqadd_s64 and friends.
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r196190 | jiangning | 2013-12-02 17:29:32 -0800 (Mon, 02 Dec 2013) | 2 lines
Add some missing pattern matches for AArch64 Neon intrinsics like vmull_high_n_s16 and friends.
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r196391 | hliao | 2013-12-04 09:44:22 -0800 (Wed, 04 Dec 2013) | 5 lines
[X86] Check YMM31/ZMM31 as well
- No test case as there's no calling convention preserve YMM31/ZMM31 only
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r196261 | hliao | 2013-12-03 01:17:32 -0800 (Tue, 03 Dec 2013) | 13 lines
Enhance the fix of PR17631
- The fix to PR17631 fixes part of the cases where 'vzeroupper' should
not be issued before 'call' insn. There're other cases where helper
calls will be inserted not limited to epilog. These helper calls do
not follow the standard calling convention and won't clobber any YMM
registers. (So far, all call conventions will clobber any or part of
YMM registers.)
This patch enhances the previous fix to cover more cases 'vzerosupper' should
not be inserted by checking if that function call won't clobber any YMM
registers and skipping it if so.
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r196269 | jamesm | 2013-12-03 03:23:11 -0800 (Tue, 03 Dec 2013) | 5 lines
Addrspacecasts are no-ops on ARM.
Testcase added.
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r196267 | rsandifo | 2013-12-03 11:01:54 +0000 (Tue, 03 Dec 2013) | 12 lines
[SystemZ] Fix choice of known-zero mask in insertion optimization
The backend converts 64-bit ORs into subreg moves if the upper 32 bits
of one operand and the low 32 bits of the other are known to be zero.
It then tries to peel away redundant ANDs from the upper 32 bits.
Since AND masks are canonicalized to exclude known-zero bits,
the test ORs the mask and the known-zero bits together before
checking for redundancy. The problem was that it was using the
wrong node when checking for known-zero bits, so could drop ANDs
that were still needed.
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r196151 | mcrosier | 2013-12-02 13:05:16 -0800 (Mon, 02 Dec 2013) | 2 lines
[AArch64] Implemented vcopy_lane patterns using scalar DUP instruction.
Patch by Ana Pazos!
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r196046 | tnorthover | 2013-12-01 06:16:24 -0800 (Sun, 01 Dec 2013) | 8 lines
ARM: fix bug in -Oz stack adjustment folding
Previously, we clobbered callee-saved registers when folding an "add
sp, #N" into a "pop {rD, ...}" instruction. This change checks whether
a register we're going to add to the "pop" could actually be live
outside the function before doing so and should fix the issue.
This should fix PR18081.
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r195401 | lhames | 2013-11-21 16:46:32 -0800 (Thu, 21 Nov 2013) | 8 lines
Fix a typo where we were creating <def,kill> operands instead of
<def,dead> ones.
Add an assertion to make sure we catch this in the future.
Fixes <rdar://problem/15464559>.
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r196044 | d0k | 2013-12-01 03:47:42 -0800 (Sun, 01 Dec 2013) | 6 lines
Revamp error checking in the ms inline asm parser.
- Actually abort when an error occurred.
- Check that the frontend lookup worked when parsing length/size/type operators.
Tested by a clang test. PR18096.
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