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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94374 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94373 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94350 91177308-0d34-0410-b5e6-96231b3b80d8
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movw $8, (_cost_table_-L97$pb)+66(%eax)
After the parens, we could still have a binop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94345 91177308-0d34-0410-b5e6-96231b3b80d8
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"sext cond" instead of a select. This simplifies some instcombine
code, matches the policy for zext (cond ? 1 : 0 -> zext), and allows
us to generate better code for a testcase on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94339 91177308-0d34-0410-b5e6-96231b3b80d8
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the alignment allows. Fixed a bug where we didn't use a
vector load/store for PR5626.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94338 91177308-0d34-0410-b5e6-96231b3b80d8
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readme forever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94318 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94317 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94312 91177308-0d34-0410-b5e6-96231b3b80d8
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the '-pre-RA-sched' flag. It actually makes more sense to do it this way. Also,
keep track of the SDNode ordering by default. Eventually, we would like to make
this ordering a way to break a "tie" in the scheduler. However, doing that now
breaks the "CodeGen/X86/abi-isel.ll" test for 32-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94308 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94299 91177308-0d34-0410-b5e6-96231b3b80d8
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a .section. Switch to it with SwitchSection.
However, I think that this directive should be safe on any ELF target.
If so, we should hoist it up out of the X86 and SystemZ targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94298 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94296 91177308-0d34-0410-b5e6-96231b3b80d8
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into a new MCDirectives.h file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94294 91177308-0d34-0410-b5e6-96231b3b80d8
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stack may be misaligned.
Update test accordingly.
Patch by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94291 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94286 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94285 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94278 91177308-0d34-0410-b5e6-96231b3b80d8
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target-specific AsmLexer, and added the appropriate
registration calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94275 91177308-0d34-0410-b5e6-96231b3b80d8
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be static. Also made it possible for clients to get it
and no other functions from ...GenAsmMatcher.inc by
defining REGISTERS_ONLY before including GenAsmMatcher.inc.
This sets the stage for target-specific lexers that can
identify registers and return AsmToken::Register as
appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94266 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94254 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94205 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94197 91177308-0d34-0410-b5e6-96231b3b80d8
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this should fix a problem duncan saw handling symbols with '.' in them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94192 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94189 91177308-0d34-0410-b5e6-96231b3b80d8
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missing ones are libsupport, libsystem and libvmcore. libvmcore is
currently blocked on bugpoint, which uses EH. Once it stops using
EH, we can switch it off.
This #if 0's out 3 unit tests, because gtest requires RTTI information.
Suggestions welcome on how to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94164 91177308-0d34-0410-b5e6-96231b3b80d8
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scheduled together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94147 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94132 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94129 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94125 91177308-0d34-0410-b5e6-96231b3b80d8
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cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94098 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94095 91177308-0d34-0410-b5e6-96231b3b80d8
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This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.
It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94061 91177308-0d34-0410-b5e6-96231b3b80d8
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unaligned load so it doesn't require 16-byte alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94058 91177308-0d34-0410-b5e6-96231b3b80d8
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this makes function stub emission determinstic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94033 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94032 91177308-0d34-0410-b5e6-96231b3b80d8
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no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94030 91177308-0d34-0410-b5e6-96231b3b80d8
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MachineModuleInfoMachO instead. This eliminates two sources
of nondeterministic output in the ppc backend, but function
stubs are still bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94029 91177308-0d34-0410-b5e6-96231b3b80d8
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points. This will help us find future problems like the one
described in PR6019.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94019 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94008 91177308-0d34-0410-b5e6-96231b3b80d8
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go completely away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93994 91177308-0d34-0410-b5e6-96231b3b80d8
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stomache MCAsmInfo having this, and I found a better solution to
this layering issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93985 91177308-0d34-0410-b5e6-96231b3b80d8
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more cases where debug declarations affect
debug line info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93953 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93940 91177308-0d34-0410-b5e6-96231b3b80d8
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line number info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93937 91177308-0d34-0410-b5e6-96231b3b80d8
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I really want clients of the streamer to be able to say "emit this
64-bit integer" and have it get broken down right by the streamer.
I may change this in the future, we'll see how it works out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93934 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93918 91177308-0d34-0410-b5e6-96231b3b80d8
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the two token accessor functions are declared consistently.
Modified the clients of MCAsmParser to reflect this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93916 91177308-0d34-0410-b5e6-96231b3b80d8
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Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
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