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* Support unaligned load/store on more ARM targetsDerek Schuff2013-05-15
| | | | | | | | | | | | | | | | | This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on other targets. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux behaves sanely). Overall this should slightly improve performance in most cases because of reduced I$ pressure. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181897 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove MCELFObjectTargetWriter::adjustFixupOffset hackUlrich Weigand2013-05-15
| | | | | | | | | | Now that PowerPC no longer uses adjustFixupOffset, and no other back-end (ever?) did, we can remove the infrastructure itself (incidentally addressing a FIXME to that effect). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181895 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Remove need for adjustFixupOffst hackUlrich Weigand2013-05-15
| | | | | | | | | | | | | | | | | | Now that applyFixup understands differently-sized fixups, we can define fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte fixups, applied at an offset of 2 relative to the start of the instruction text. This has the benefit that if we actually need to generate a real relocation record, its address will come out correctly automatically, without having to fiddle with the offset in adjustFixupOffset. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-15
| | | | | | | Thanks to Ulrich Weigand for noticing that this instruction was missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Correctly handle fixups of other than 4 byte sizeUlrich Weigand2013-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PPCAsmBackend::applyFixup routine handles the case where a fixup can be resolved within the same object file. However, this routine is currently hard-coded to assume the size of any fixup is always exactly 4 bytes. This is sort-of correct for fixups on instruction text; even though it only works because several of what really would be 2-byte fixups are presented as 4-byte fixups instead (requiring another hack in PPCELFObjectWriter::adjustFixupOffset to clean it up). However, this assumption breaks down completely for fixups on data, which legitimately can be of any size (1, 2, 4, or 8). This patch makes applyFixup aware of fixups of varying sizes, introducing a new helper routine getFixupKindNumBytes (along the lines of what the ARM back end does). Note that in order to handle fixups of size 8, we also need to fix the return type of adjustFixupValue to uint64_t to avoid truncation. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181891 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add more future work items to the READMERichard Sandiford2013-05-15
| | | | | | | Based on an analysis by Ulrich Weigand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181882 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix build on WindowsTimur Iskhodzhanov2013-05-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181873 91177308-0d34-0410-b5e6-96231b3b80d8
* Use only explicit bool conversion operatorsDavid Blaikie2013-05-15
| | | | | | | | | | | | | | | | | | | | | | | BitVector/SmallBitVector::reference::operator bool remain implicit since they model more exactly a bool, rather than something else that can be boolean tested. The most common (non-buggy) case are where such objects are used as return expressions in bool-returning functions or as boolean function arguments. In those cases I've used (& added if necessary) a named function to provide the equivalent (or sometimes negative, depending on convenient wording) test. One behavior change (YAMLParser) was made, though no test case is included as I'm not sure how to reach that code path. Essentially any comparison of llvm::yaml::document_iterators would be invalid if neither iterator was at the end. This helped uncover a couple of bugs in Clang - test cases provided for those in a separate commit along with similar changes to `operator bool` instances in Clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181868 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: Fix commentsArnold Schwaighofer2013-05-15
| | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181862 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: Hoist conditional loads if possibleArnold Schwaighofer2013-05-15
| | | | | | | | | | | | InstCombine can be uncooperative to vectorization and sink loads into conditional blocks. This prevents vectorization. Undo this optimization if there are unconditional memory accesses to the same addresses in the loop. radar://13815763 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181860 91177308-0d34-0410-b5e6-96231b3b80d8
* Speed up Value::isUsedInBasicBlock() for long use lists.Jakob Stoklund Olesen2013-05-14
| | | | | | | | | | | | | | | | This is expanding Ben's original heuristic for short basic blocks to also work for longer basic blocks and huge use lists. Scan the basic block and the use list in parallel, terminating the search when the shorter list ends. In almost all cases, either the basic block or the use list is short, and the function returns quickly. In one crazy test case with very long use chains, CodeGenPrepare runs 400x faster. When compiling ARMDisassembler.cpp it is 5x faster. <rdar://problem/13840497> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181851 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two typoSylvestre Ledru2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181848 91177308-0d34-0410-b5e6-96231b3b80d8
* Object: Fix Mach-O relocation printing.Ahmed Bougacha2013-05-14
| | | | | | | | | | There were two problems that made llvm-objdump -r crash: - for non-scattered relocations, the symbol/section index is actually in the (aptly named) symbolnum field. - sections are 1-indexed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181843 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM ISel: Don't create illegal types during LowerMULArnold Schwaighofer2013-05-14
| | | | | | | | | | | | | | | | | The transformation happening here is that we want to turn a "mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have to make sure that X still has a valid vector type - possibly recreate an extension to a smaller type. In case of a extload of a memory type smaller than 64 bit we used create a ext(load()). The problem with doing this - instead of recreating an extload - is that an illegal type is exposed. This patch fixes this by creating extloads instead of ext(load()) sequences. Fixes PR15970. radar://13871383 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181842 91177308-0d34-0410-b5e6-96231b3b80d8
* GlobalOpt: fix an issue where CXAAtExitFn points to a deleted function.Manman Ren2013-05-14
| | | | | | | | | | | | CXAAtExitFn was set outside a loop and before optimizations where functions can be deleted. This patch will set CXAAtExitFn inside the loop and after optimizations. Seg fault when running LTO because of accesses to a deleted function. rdar://problem/13838828 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181838 91177308-0d34-0410-b5e6-96231b3b80d8
* Make getCompileUnit non-const and return the current DIE if itEric Christopher2013-05-14
| | | | | | | happens to be a compile unit. Noticed on inspection and tested via calling on a newly created compile unit. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181835 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the PowerPC system call (sc) instruction.Bill Schmidt2013-05-14
| | | | | | | Instruction added at request of Roman Divacky. Tested via asm-parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181821 91177308-0d34-0410-b5e6-96231b3b80d8
* SectionMemoryManager shouldn't be a JITMemoryManager. Previously, the Filip Pizlo2013-05-14
| | | | | | | | | | | | | | | | | | | EngineBuilder interface required a JITMemoryManager even if it was being used to construct an MCJIT. But the MCJIT actually wants a RTDyldMemoryManager. Consequently, the SectionMemoryManager, which is meant for MCJIT, derived from the JITMemoryManager and then stubbed out a bunch of JITMemoryManager methods that weren't relevant to the MCJIT. This patch fixes the situation: it teaches the EngineBuilder that RTDyldMemoryManager is a supertype of JITMemoryManager, and that it's appropriate to pass a RTDyldMemoryManager instead of a JITMemoryManager if we're using the MCJIT. This allows us to remove the stub methods from SectionMemoryManager, and make SectionMemoryManager a direct subtype of RTDyldMemoryManager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181820 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Pass to replace tranfer/copy instructions into combine instructionJyotsna Verma2013-05-14
| | | | | | | | where possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply "Subtract isn't commutative, fix this for MMX psub." withEric Christopher2013-05-14
| | | | | | | a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181814 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert "Subtract isn't commutative, fix this for MMX psub."Eric Christopher2013-05-14
| | | | | | It's causing failures on the atom bot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181812 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix __clear_cache declaration.Rafael Espindola2013-05-14
| | | | | | This fixes the build with gcc in gnu++98 and gnu++11 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181811 91177308-0d34-0410-b5e6-96231b3b80d8
* Subtract isn't commutative, fix this for MMX psub.Eric Christopher2013-05-14
| | | | | | Patch by Andrea DiBiagio. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181809 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize sparc64 as an alias for sparcv9 triples.Jakob Stoklund Olesen2013-05-14
| | | | | | Patch by Brad Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181808 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bitcast to store of personality function.Kai Nacke2013-05-14
| | | | | | | | | | The personality function is user defined and may have an arbitrary result type. The code assumes always i8*. This results in an assertion failure if a different type is used. A bitcast to i8* is added to prevent this failure. Reviewed by: Renato Golin, Bob Wilson git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181802 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC32: Fix stack collision between FP and CR save areas.Bill Schmidt2013-05-14
| | | | | | | | | | | | | | | | | | The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181800 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove dead-code after unconditional return from addPreSched2.Jyotsna Verma2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add processor type for Hainan asicTom Stellard2013-05-14
| | | | | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181792 91177308-0d34-0410-b5e6-96231b3b80d8
* Declare __clear_cache.Rafael Espindola2013-05-14
| | | | | | | | GCC declares __clear_cache in the gnu modes (-std=gnu++98, -std=gnu++11), but not in the strict modes (-std=c++98, -std=c++11). This patch declares it and therefore fixes the build when using one of the strict modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181785 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add disassembler supportRichard Sandiford2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rework handling of constant PC-relative operandsRichard Sandiford2013-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GNU assembler treats things like: brasl %r14, 100 in the same way as: brasl %r14, .+100 rather than as a branch to absolute address 100. We implemented this in LLVM by creating an immediate operand rather than the usual expr operand, and by handling immediate operands specially in the code emitter. This was undesirable for (at least) three reasons: - the specialness of immediate operands was exposed to the backend MC code, rather than being limited to the assembler parser. - in disassembly, an immediate operand really is an absolute address. (Note that this means reassembling printed disassembly can't recreate the original code.) - it would interfere with any assembly manipulation that we might try in future. E.g. operations like branch shortening can change the relative position of instructions, but any code that updates sym+offset addresses wouldn't update an immediate "100" operand in the same way as an explicit ".+100" operand. This patch changes the implementation so that the assembler creates a "." label for immediate PC-relative operands, so that the operand to the MCInst is always the absolute address. The patch also adds some error checking of the offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181773 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Remove bogus isAsmParserOnlyRichard Sandiford2013-05-14
| | | | | | | | | | | Marking instructions as isAsmParserOnly stops them from being disassembled. However, in cases where separate asm and codegen versions exist, we actually want to disassemble to the asm ones. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181772 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181771 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181769 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed trailing whitespace.Michael Gottesman2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181760 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo.Reed Kotler2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181759 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed an unnamed namespace and forgot to make two of the functions insideReed Kotler2013-05-14
| | | | | | | | "static". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the first of three patches which creates stubs used forReed Kotler2013-05-14
| | | | | | | | | | | | | | | | | | | | | | | | | Mips16/32 floating point interoperability. When Mips16 code calls external functions that would normally have some of its parameters or return values passed in floating point registers, it needs (Mips32) helper functions to do this because while in Mips16 mode there is no ability to access the floating point registers. In Pic mode, this is done with a set of predefined functions in libc. This case is already handled in llvm for Mips16. In static relocation mode, for efficiency reasons, the compiler generates stubs that the linker will use if it turns out that the external function is a Mips32 function. (If it's Mips16, then it does not need the helper stubs). These stubs are identically named and the linker knows about these tricks and will not create multiple copies and will delete them if they are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8
* StackColoring: don't clear an instruction's mem operand if the underlyingAkira Hatanaka2013-05-14
| | | | | | | | | object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e., points to memory that has a constant value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181751 91177308-0d34-0410-b5e6-96231b3b80d8
* Assert that DIEEntries are constructed with non-null DIEsDavid Blaikie2013-05-14
| | | | | | | This just brings a crash a little further forward from DWARF emission to DIE construction to make errors easier to diagnose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181748 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: Handle loops with multiple forward inductionsArnold Schwaighofer2013-05-14
| | | | | | | | | | | | We used to give up if we saw two integer inductions. After this patch, we base further induction variables on the chosen one like we do in the reverse induction and pointer induction case. Fixes PR15720. radar://13851975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181746 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc-opts] Added debug statements when we set and unset whether a ↵Michael Gottesman2013-05-14
| | | | | | pointer is known positive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181745 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs ↵Michael Gottesman2013-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if and only if we are both KnownSafeBU/KnownSafeTD rather than just either or. In the presense of a block being initialized, the frontend will emit the objc_retain on the original pointer and the release on the pointer loaded from the alloca. The optimizer will through the provenance analysis realize that the two are related (albiet different), but since we only require KnownSafe in one direction, will match the inner retain on the original pointer with the guard release on the original pointer. This is fixed by ensuring that in the presense of allocas we only unconditionally remove pointers if both our retain and our release are KnownSafe (i.e. we are KnownSafe in both directions) since we must deal with the possibility that the frontend will emit what (to the optimizer) appears to be unbalanced retain/releases. An example of the miscompile is: %A = alloca retain(%x) retain(%x) <--- Inner Retain store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) release(%x) <--- Guarding Release getting optimized to: %A = alloca retain(%x) store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) rdar://13750319 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181743 91177308-0d34-0410-b5e6-96231b3b80d8
* Move a couple more statistics inside '#ifndef NDEBUG'.Matt Beaumont-Gay2013-05-13
| | | | | | Suppresses an unused-variable warning in -Asserts builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181733 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Assembler macro ADDIU $rs,immJack Carter2013-05-13
| | | | | | | | | | | | | | | | This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc-opts] Add comment to BBState making it clear that ↵Michael Gottesman2013-05-13
| | | | | | get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181726 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix goofy commentary in PPCTargetObjectFile.cpp.Bill Schmidt2013-05-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.Bill Schmidt2013-05-13
| | | | | | | | | | | | | | | | | | | | | | This fixes warning messages observed in the oggenc application test in projects/test-suite. Special handling is needed for the 64-bit PowerPC SVR4 ABI when a constant is initialized with a pointer to a function in a shared library. Because a function address is implemented as the address of a function descriptor, the use of copy relocations can lead to problems with initialization. GNU ld therefore replaces copy relocations with dynamic relocations to be resolved by the dynamic linker. This means the constant cannot reside in the read-only data section, but instead belongs in .data.rel.ro, which is designed for constants containing dynamic relocations. The implementation creates a class PPC64LinuxTargetObjectFile inheriting from TargetLoweringObjectFileELF, which behaves like its parent except to place constants of this sort into .data.rel.ro. The test case is reduced from the oggenc application. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8
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