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| * Move a couple more statistics inside '#ifndef NDEBUG'.Matt Beaumont-Gay2013-05-13
| | | | | | | | | | | | Suppresses an unused-variable warning in -Asserts builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181733 91177308-0d34-0410-b5e6-96231b3b80d8
| * Mips assembler: Assembler macro ADDIU $rs,immJack Carter2013-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
| * [objc-arc-opts] Add comment to BBState making it clear that ↵Michael Gottesman2013-05-13
| | | | | | | | | | | | get{TopDown,BottomUp}PtrState will create a new PtrState object if it does not find a PtrState for Arg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181726 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix goofy commentary in PPCTargetObjectFile.cpp.Bill Schmidt2013-05-13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8
| * PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.Bill Schmidt2013-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes warning messages observed in the oggenc application test in projects/test-suite. Special handling is needed for the 64-bit PowerPC SVR4 ABI when a constant is initialized with a pointer to a function in a shared library. Because a function address is implemented as the address of a function descriptor, the use of copy relocations can lead to problems with initialization. GNU ld therefore replaces copy relocations with dynamic relocations to be resolved by the dynamic linker. This means the constant cannot reside in the read-only data section, but instead belongs in .data.rel.ro, which is designed for constants containing dynamic relocations. The implementation creates a class PPC64LinuxTargetObjectFile inheriting from TargetLoweringObjectFileELF, which behaves like its parent except to place constants of this sort into .data.rel.ro. The test case is reduced from the oggenc application. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove redundant variable introduced by r181682.Bob Wilson2013-05-13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181721 91177308-0d34-0410-b5e6-96231b3b80d8
| * [objc-arc] Move the before optimization statistics gathering phase out of ↵Michael Gottesman2013-05-13
| | | | | | | | | | | | | | | | | | | | | | OptimizeIndividualCalls. This makes the statistics gathering completely independent of the actual optimization occuring, preventing any sort of bleeding over from occuring. Additionally, it simplifies a switch statement in the non-statistic gathering case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181719 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-13
| | | | | | | | | | | | | | | | | | This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix a bug that APFloat::fusedMultiplyAdd() mistakenly evaluate "14.5f * ↵Shuxin Yang2013-05-13
| | | | | | | | | | | | -14.5f + 225.0f" to 225.0f. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181715 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Define a helper function which creates an instruction with the sameAkira Hatanaka2013-05-13
| | | | | | | | | | | | | | | | operands as the prototype instruction but with a different opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unused fields and arguments.Rafael Espindola2013-05-13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8
| * The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-13
| | | | | | | | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8
| * Correctly preserve the input chain for potential tailcall nodes whoseLang Hames2013-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | return values are bitcasts. The chain had previously been being clobbered with the entry node to the dag, which sometimes caused other code in the function to be erroneously deleted when tailcall optimization kicked in. <rdar://problem/13827621> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181696 91177308-0d34-0410-b5e6-96231b3b80d8
| * Suppress GCC compiler warnings in release builds about variables that are onlyDuncan Sands2013-05-13
| | | | | | | | | | | | | | read in asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8
| * SLPVectorizer: Swap LHS and RHS. No functionality change.Nadav Rotem2013-05-13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181684 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix PR15950 A bug in DAG Combiner about undef maskHao Liu2013-05-13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181682 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove the MachineMove class.Rafael Espindola2013-05-13
| | | | | | | | | | | | | | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
| * SLPVectorizer: Fix a bug in the code that generates extracts for values with ↵Nadav Rotem2013-05-12
| | | | | | | | | | | | | | | | | | | | multiple users. The external user does not have to be in lane #0. We have to save the lane for each scalar so that we know which vector lane to extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181674 91177308-0d34-0410-b5e6-96231b3b80d8
| * SLPVectorizer: Clear the map that maps between scalars to vectors after each ↵Nadav Rotem2013-05-12
| | | | | | | | | | | | | | | | | | | | round of vectorization. Testcase in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181673 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge branch 'master' into embtk-support-masterAbdoulaye Walsimou Gaye2013-05-12
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| * InstCombine: Flip the order of two urem transformsDavid Majnemer2013-05-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two transforms in visitUrem that conflict with each other. *) One, if a divisor is a power of two, subtracts one from the divisor and turns it into a bitwise-and. *) The other unwraps both operands if they are surrounded by zext instructions. Flipping the order allows the subtraction to go beneath the sign extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181668 91177308-0d34-0410-b5e6-96231b3b80d8
| * LoopVectorize: Use the widest induction variable typeArnold Schwaighofer2013-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the widest induction type encountered for the cannonical induction variable. We used to turn the following loop into an empty loop because we used i8 as induction variable type and truncated 1024 to 0 as trip count. int a[1024]; void fail() { int reverse_induction = 1023; unsigned char forward_induction = 0; while ((reverse_induction) >= 0) { forward_induction++; a[reverse_induction] = forward_induction; --reverse_induction; } } radar://13862901 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181667 91177308-0d34-0410-b5e6-96231b3b80d8
| * LoopVectorize: Use variable instead of repeated function callArnold Schwaighofer2013-05-11
| | | | | | | | | | | | No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181666 91177308-0d34-0410-b5e6-96231b3b80d8
| * LoopVectorize: Use IRBuilder interface in more placesArnold Schwaighofer2013-05-11
| | | | | | | | | | | | No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181665 91177308-0d34-0410-b5e6-96231b3b80d8
| * StringRefize some debug accel table bits.Benjamin Kramer2013-05-11
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181663 91177308-0d34-0410-b5e6-96231b3b80d8
| * InstCombine: Turn urem to bitwise-and more oftenDavid Majnemer2013-05-11
| | | | | | | | | | | | | | | | Use isKnownToBeAPowerOfTwo in visitUrem so that we may more aggressively fold away urem instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181661 91177308-0d34-0410-b5e6-96231b3b80d8
| * Change getFrameMoves to return a const reference.Rafael Espindola2013-05-11
| | | | | | | | | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove more dead code.Rafael Espindola2013-05-11
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181656 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove dead code.Rafael Espindola2013-05-10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181649 91177308-0d34-0410-b5e6-96231b3b80d8
| * SLPVectorizer: Add support for trees with external users.Nadav Rotem2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For example: bar() { int a = A[i]; int b = A[i+1]; B[i] = a; B[i+1] = b; foo(a); <--- a is used outside the vectorized expression. } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181648 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a debug printNadav Rotem2013-05-10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181647 91177308-0d34-0410-b5e6-96231b3b80d8
| * Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
| * Micro-optimization: don't shift an entire bitcode record over to get the code.Jordan Rose2013-05-10
| | | | | | | | | | | | | | | | | | | | | | Previously, BitstreamCursor read an abbreviated record by splatting the whole thing into a data vector, then extracting and removing the /first/ element. Now, it reads the first element--the record code--separately from the actual field values. No (intended) functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181639 91177308-0d34-0410-b5e6-96231b3b80d8
| * PR14492: Debug Info: Support for values of non-integer non-type template ↵David Blaikie2013-05-10
| | | | | | | | | | | | | | | | | | | | parameters. This is only tested for global variables at the moment (& includes tests for the unnamed parameter case, since apparently this entire function was completely untested previously) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181632 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix unused variable error.Jyotsna Verma2013-05-10
| | | | | | | | | | | | | | | | | | Earlier, this variable was used in an assert and was causing failure on darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181630 91177308-0d34-0410-b5e6-96231b3b80d8
| * Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-10
| | | | | | | | | | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181628 91177308-0d34-0410-b5e6-96231b3b80d8
| * Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix the R600 build.Rafael Espindola2013-05-10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181621 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ms-inline asm] Fix a crasher when we fail on a direct match.Chad Rosier2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181620 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unused argument.Rafael Espindola2013-05-10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
| * Better output for long help strings for command-line options.Alexander Kornienko2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch allows using \n inside long help strings for command-line options, so that all lines are equally indented. This is not a perfect solution, as we don't (and probably don't want to) know about terminal width, but it allows to format long help strings somehow readable without manually padding them with spaces. A motivating example is -help output from clang-format (source code in tools/clang-format/ClangFormat.cpp, see cl options offset, length, style, and dump-config). Reviewers: atrick, alexfh Reviewed By: alexfh CC: llvm-commits, rafael Differential Revision: http://llvm-reviews.chandlerc.com/D779 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181608 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unused function.Rafael Espindola2013-05-10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181606 91177308-0d34-0410-b5e6-96231b3b80d8
| * InstCombine: Don't claim to be able to evaluate any shl in a zexted type.Benjamin Kramer2013-05-10
| | | | | | | | | | | | | | | | | | | | The shift amount may be larger than the type leading to undefined behavior. Limit the transform to constant shift amounts. While there update the bits to clear in the result which may enable additional optimizations. PR15959. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181604 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implement AsmParser for ARM unwind directives.Logan Chien2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements the AsmParser for fnstart, fnend, cantunwind, personality, handlerdata, pad, setfp, save, and vsave directives. This commit fixes some minor issue in the ARMELFStreamer: * The switch back to corresponding section after the .fnend directive. * Emit the unwind opcode while processing .fnend directive if there is no .handlerdata directive. * Emit the unwind opcode to .ARM.extab while processing .handlerdata even if .personality directive does not exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181603 91177308-0d34-0410-b5e6-96231b3b80d8
| * DAGCombiner: Generate a correct constant for vector types when folding (xor ↵Benjamin Kramer2013-05-10
| | | | | | | | | | | | | | | | (and)) into (and (not)). PR15948. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181597 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge branch 'master' into embtk-support-masterAbdoulaye Walsimou Gaye2013-05-10
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| * InstCombine: Verify the type before transforming uitofp into select.Benjamin Kramer2013-05-10
| | | | | | | | | | | | PR15952. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181586 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ↵Tom Stellard2013-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181580 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600: Expand SUB for v2i32/v4i32Tom Stellard2013-05-10
| | | | | | | | | | | | | | | | | | | | | | Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181579 91177308-0d34-0410-b5e6-96231b3b80d8
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