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* Add PPC instruction record forms and associated query functionsHal Finkel2013-04-12
| | | | | | | | | | | | | | | | | | This is prep. work for the implementation of optimizeCompare. Many PPC instructions have 'record' forms (in almost all cases, this means that the RC bit is set) that cause the result of the instruction to be compared with zero, and the result of that comparison saved in a predefined condition register. In order to add the record forms of the instructions without too much copy-and-paste, the relevant functions have been refactored into multiclasses which define both the record and normal forms. Also, two TableGen-generated mapping functions have been added which allow querying the instruction code for the record form given the normal form (and vice versa). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179356 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't disable block layout when forcing block alignment.Nadav Rotem2013-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179355 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag to align all basic blocks in the function.Nadav Rotem2013-04-12
| | | | | | | | | | | | When debugging performance regressions we often ask ourselves if the regression that we see is due to poor isel/sched/ra or due to some micro-architetural problem. When comparing two code sequences one good way to rule out front-end bottlenecks (and other the issues) is to force code alignment. This pass adds a flag that forces the alignment of all of the basic blocks in the program. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179353 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 179294 back, but don't use bit fields so that it works on big endian hosts.Rafael Espindola2013-04-12
| | | | | | | | | | | | | | Original message: Print more information about relocations. With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179345 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for using the LENGTH, TYPE, and SIZE operators withChad Rosier2013-04-11
| | | | | | | | | variables that use namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179343 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for using offsetof operator with variables that useChad Rosier2013-04-11
| | | | | | | | namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179339 91177308-0d34-0410-b5e6-96231b3b80d8
* Aliasing rules for struct-path aware TBAA.Manman Ren2013-04-11
| | | | | | | | Added PathAliases to check if two struct-path tags can alias. Added command line option -struct-path-tbaa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179337 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Pass a StringRef reference to ParseIntelVarWithQualifier so weChad Rosier2013-04-11
| | | | | | | | | can build up the identifier string. No test case as support for looking up these type of identifiers hasn't been implemented on the clang side. Part of rdar://13499009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179336 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Remove brackets from around a symbol reference in the targetChad Rosier2013-04-11
| | | | | | | | | specific logic. This makes the code much less fragile. Test case coming on the clang side in a moment. rdar://13634327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179323 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix undefined behavior in AArch64David Majnemer2013-04-11
| | | | | | | | | A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to execute shifts that perform undefined behavior. Instead of attempting to perform the 64-bit rotation, treat it as a no-op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179317 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize icmp involving addition betterDavid Majnemer2013-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | Allows LLVM to optimize sequences like the following: %add = add nsw i32 %x, 1 %cmp = icmp sgt i32 %add, %y into: %cmp = icmp sge i32 %x, %y as well as: %add1 = add nsw i32 %x, 20 %add2 = add nsw i32 %y, 57 %cmp = icmp sge i32 %add1, %add2 into: %add = add nsw i32 %y, 37 %cmp = icmp sle i32 %cmp, %x git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179316 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selectsAkira Hatanaka2013-04-11
| | | | | | | | | | multiply instructions in MipsSEDAGToDAGISel. This patch was supposed to be part of r178403. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179314 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.Akira Hatanaka2013-04-11
| | | | | | | | | | | - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179312 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert my last two commits while I debug what is wrong in a big endian host.Rafael Espindola2013-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179303 91177308-0d34-0410-b5e6-96231b3b80d8
* Print more information about relocations.Rafael Espindola2013-04-11
| | | | | | | | | | With this patch llvm-readobj now prints if a relocation is pcrel, its length, if it is extern and if it is scattered. It also refactors the code a bit to use bit fields instead of shifts and masks all over the place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179294 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for wrong instcombine on vector insert/extractBenjamin Kramer2013-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When trying to collapse sequences of insertelement/extractelement instructions into single shuffle instructions, there is one specific case where the Instruction Combiner wrongly updates the resulting Mask of shuffle indexes. The problem is in function CollectShuffleElments. If we have a sequence of insert/extract element instructions like the one below: %tmp1 = extractelement <4 x float> %LHS, i32 0 %tmp2 = insertelement <4 x float> %RHS, float %tmp1, i32 1 %tmp3 = extractelement <4 x float> %RHS, i32 2 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 3 Where: . %RHS will have a mask of [4,5,6,7] . %LHS will have a mask of [0,1,2,3] The Mask of shuffle indexes is wrongly computed to [4,1,6,7] instead of [4,0,6,7]. When analyzing %tmp2 in order to compute the Mask for the resulting shuffle instruction, the algorithm forgets to update the mask index at position 1 with the index associated to the element extracted from %LHS by instruction %tmp1. Patch by Andrea DiBiagio! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179291 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a function to check if an argument list is too long.Rafael Espindola2013-04-11
| | | | | | | | | This will be used in clang to decide if it should create an @file or not. It will be tested on the clang side. Patch by Nathan Froyd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179285 91177308-0d34-0410-b5e6-96231b3b80d8
* [ASan] Allow disabling init-order checks for globals by source file name.Alexey Samsonov2013-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179280 91177308-0d34-0410-b5e6-96231b3b80d8
* Add braces around || in && to pacify GCC.Benjamin Kramer2013-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179275 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the C function to create a SLPVectorizerPass to something sane and ↵Benjamin Kramer2013-04-11
| | | | | | expose it in the header file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179272 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize vector select from all 0s or all 1sMichael Liao2013-04-11
| | | | | | | | | | As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-11
| | | | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance bool simplifcation in X86 to handle more casesMichael Liao2013-04-11
| | | | | | | | | | | | | | This patch is revised based on patch from Victor Umansky <victor.umansky@intel.com>. More cases are handled in X86's bool simplification, i.e. - SETCC_CARRY - value is truncated to i1 with AND As a by-product, PR5443 is also fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
* R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179263 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.NAKAMURA Takumi2013-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179262 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MachO's getRelocationAdditionalInfo.Rafael Espindola2013-04-11
| | | | | | | It was returning the loaded address of the section containing the relocation, which really doesn't seem to be the intent of this function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179255 91177308-0d34-0410-b5e6-96231b3b80d8
* Make PPCInstrInfo::isPredicated always return falseHal Finkel2013-04-11
| | | | | | | Because of how predication in implemented on PPC (only for branches), I think that this is the right thing to do. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179252 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Support COFF image-relative MCSymbolRefsNico Rieck2013-04-10
| | | | | | | | | | | | | | | | Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are similar to normal 4-byte relocations except that they do not include the base address of the image. Image-relative relocations are used for debug information (32-bit) and SEH unwind tables (64-bit). A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to specify such relocations. For AT&T assembly, this variant can be accessed using the symbol suffix '@imgrel'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8
* Manually remove successors in if conversion when CopyAndPredicateBlock is usedHal Finkel2013-04-10
| | | | | | | | | | | | | | | In the simple and triangle if-conversion cases, when CopyAndPredicateBlock is used because the to-be-predicated block has other predecessors, we need to explicitly remove the old copied block from the successors list. Normally if conversion relies on TII->AnalyzeBranch combined with BB->CorrectExtraCFGEdges to cleanup the successors list, but if the predicated block contained an un-analyzable branch (such as a now-predicated return), then this will fail. These extra successors were causing a problem on PPC because it was causing later passes (such as PPCEarlyReturm) to leave dead return-only basic blocks in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179227 91177308-0d34-0410-b5e6-96231b3b80d8
* No need to have this return a bool.Bill Wendling2013-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179226 91177308-0d34-0410-b5e6-96231b3b80d8
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
* Track the compact unwind encoding for when we are unable to generate compact ↵Bill Wendling2013-04-10
| | | | | | | | | | | unwind information. Compact unwind has an encoding for when we're not able to generate compact unwind and must generate an EH frame instead. Track that, but still emit that CU encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179220 91177308-0d34-0410-b5e6-96231b3b80d8
* fixed to disassemble with tab after mnemonic rather than spaceKay Tiong Khoo2013-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179215 91177308-0d34-0410-b5e6-96231b3b80d8
* In the X86 back end, getMemoryOperandNo() returns the offsetPreston Gurd2013-04-10
| | | | | | | | | | | | | | into the operand array of the start of the memory reference descriptor. Additional code in EncodeInstruction provides an additional adjustment. This patch places that additional code in a separate function, called getOperandBias, so that any caller of getMemoryOperandNo can also call getOperandBias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179211 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up, fix and simplify a few of the SMLocs. Prior to r179109 the Start SMLocChad Rosier2013-04-10
| | | | | | | | | wasn't always the start of the operand. If there was a symbol reference, then Start pointed to that token. It's very likely there are other places that need to be updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179210 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the SLP store-merger less paranoid about function calls. We check for ↵Nadav Rotem2013-04-10
| | | | | | function calls when we check if it is safe to sink instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179207 91177308-0d34-0410-b5e6-96231b3b80d8
* We require DataLayout for analyzing the size of stores.Nadav Rotem2013-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179206 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variable.Chad Rosier2013-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179205 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Don't predicate a diamond with two counter decrementsHal Finkel2013-04-10
| | | | | | | | | | I've not seen this happen in practice, and probably can't until we start allowing decrement-counter-based conditional branches to be double predicated, but just in case, don't allow predication of a diamond in which both sides have ctr-defining branches. Even though the branching behavior of these can be predicated, the counter-decrementing behavior cannot be. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179199 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r179115, but use parsePrimaryExpression a little more judiciously.Chad Rosier2013-04-10
| | | | | | | | | | | | | | | | | Test cases that regressed due to r179115, plus a few more, were added in r179182. Original commit message below: [ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to parse an identifier. Otherwise, parseExpression may parse multiple tokens, which makes it impossible to properly compute an immediate displacement. An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in the below example: __asm mov eax, [Symbol + ImmDisp] Part of rdar://13611297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179187 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for AMDGPUurecipMichel Danzer2013-04-10
| | | | | | | | 21 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179186 91177308-0d34-0410-b5e6-96231b3b80d8
* This is for an experimental option -mips-os16. The idea is to compile allReed Kotler2013-04-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this would happen as long as floating point instructions are not needed. Probably it would also make sense to compile as mips32 if atomic operations are needed too. There may be other cases too. A module pass prescans the IR and adds the mips16 or nomips16 attribute to functions depending on the functions needs. Mips 16 mode can result in a 40% code compression by utililizing 16 bit encoding of many instructions. The hope is for this to replace the traditional gcc way of dealing with Mips16 code using floating point which involves essentially using soft float but with a library implemented using mips32 floating point. This gcc method also requires creating stubs so that Mips32 code can interact with these Mips 16 functions that have floating point needs. My conjecture is that in reality this traditional gcc method would never win over this new method. I will be implementing the traditional gcc method also. Some of it is already done but I needed to do the stubs to finish the work and those required this mips16/32 mixed mode capability. I have more ideas for to make this new method much better and I think the old method will just live in llvm for anyone that needs the backward compatibility but I don't for what reason that would be needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179185 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a scheme closer to that of GNU as when deciding the type of aPeter Collingbourne2013-04-10
| | | | | | | | symbol with multiple .type declarations. Differential Revision: http://llvm-reviews.chandlerc.com/D607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179184 91177308-0d34-0410-b5e6-96231b3b80d8
* Template MachOObjectFile over endianness too.Rafael Espindola2013-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179179 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addrVincent Lejeune2013-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179174 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-10
| | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
* Change CloneFunctionInto to always clone Argument attributes induvidually,Joey Gouly2013-04-10
| | | | | | | | rather than checking if the source and destination have the same number of arguments and copying the attributes over directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179169 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: dynamical figure out the reg class of MIMGChristian Konig2013-04-10
| | | | | | | | | Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: adjust writemask to only the used componentsChristian Konig2013-04-10
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: remove image sample writemaskChristian Konig2013-04-10
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8
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