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* llvm-readobj: add support for PE32+ (Windows 64 bit executable).Rui Ueyama2014-01-26
| | | | | | | | | | | | PE32+ supports 64 bit address space, but the file format remains 32 bit. So its file format is pretty similar to PE32 (32 bit executable). The differences compared to PE32 are (1) the lack of "BaseOfData" field and (2) some of its data members are 64 bit. In this patch, I added a new member function to get a PE32+ Header object to COFFObjectFile class and made llvm-readobj to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200117 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement pattern match from v1xx to v1xx for AArch64 Neon.Jiangning Liu2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200113 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for sparc relocation types in ELF object file.Venkatraman Govindaraju2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200112 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Add patterns for concat_vector on v2i32.Kevin Qin2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200111 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix pattern match failed on FP_ROUND from v1f128 to v1f64.Kevin Qin2014-01-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200109 91177308-0d34-0410-b5e6-96231b3b80d8
* Set displacementSize to 1 for instrucitons with mod==0x1. Fixes PR17310. ↵Craig Topper2014-01-25
| | | | | | Modified from patch by James Courtier-Dutton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200100 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up hack which is no longer needed after r198617. No functionality change.Evan Cheng2014-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200095 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the use of TBAA when using AA in CodeGenHal Finkel2014-01-25
| | | | | | | | | | | | | | | | | There are currently two issues, of which I currently know, that prevent TBAA from being correctly usable in CodeGen: 1. Stack coloring does not update TBAA when merging allocas. This is easy enough to fix, but is not the largest problem. 2. CGP inserts ptrtoint/inttoptr pairs when sinking address computations. Because BasicAA does not handle inttoptr, we'll often miss basic type punning idioms that we need to catch so we don't miscompile real-world code (like LLVM). I don't yet have a small test case for this, but this fixes self hosting a non-asserts build of LLVM on PPC64 when using -enable-aa-sched-mi and -misched=shuffle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200093 91177308-0d34-0410-b5e6-96231b3b80d8
* Add combiner-aa-only-func (debug only)Hal Finkel2014-01-25
| | | | | | | | | This option (which is !NDEBUG only) allows restricting the use of alias analysis in DAGCombiner to a specific function. This has proved extremely valuable to isolating bugs related to this feature, and mirrors the misched-only-func option provided by the new instruction scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200088 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve descriptions of combiner-alias-analysis and ↵Hal Finkel2014-01-25
| | | | | | combiner-global-alias-analysis git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200087 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting r199886 (Prevent repetitive warnings for unrecognized processors ↵Artyom Skrobov2014-01-25
| | | | | | and features) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200083 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts commit r200064 and r200051.Rafael Espindola2014-01-25
| | | | | | | | | | | | | | | | | | | r200064 depends on r200051. r200051 is broken: I tries to replace .mips_hack_elf_flags, which is a good thing, but what it replaces it with is even worse. The new emitMipsELFFlags it adds corresponds to no assembly directive, is not marked as a hack and is not even printed to the .s file. The patch also introduces more uses of hasRawTextSupport. The correct way to remove .mips_hack_elf_flags is to have the mips target streamer handle the default flags (and command line options). That way the same code path is used for asm and obj. The streamer interface should *really* correspond to what is printed in the .s file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200078 91177308-0d34-0410-b5e6-96231b3b80d8
* [LPM] Conclude my immediate work by making the LoopVectorizerChandler Carruth2014-01-25
| | | | | | | | | | | | a FunctionPass. With this change the loop vectorizer no longer is a loop pass and can readily depend on function analyses. In particular, with this change we no longer have to form a loop pass manager to run the loop vectorizer which simplifies the entire pass management of LLVM. The next step here is to teach the loop vectorizer to leverage profile information through the profile information providing analysis passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200074 91177308-0d34-0410-b5e6-96231b3b80d8
* [LPM] Make LCSSA a utility with a FunctionPass that applies it to allChandler Carruth2014-01-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the loops in a function, and teach LICM to work in the presance of LCSSA. Previously, LCSSA was a loop pass. That made passes requiring it also be loop passes and unable to depend on function analysis passes easily. It also caused outer loops to have a different "canonical" form from inner loops during analysis. Instead, we go into LCSSA form and preserve it through the loop pass manager run. Note that this has the same problem as LoopSimplify that prevents enabling its verification -- loop passes which run at the end of the loop pass manager and don't preserve these are valid, but the subsequent loop pass runs of outer loops that do preserve this pass trigger too much verification and fail because the inner loop no longer verifies. The other problem this exposed is that LICM was completely unable to handle LCSSA form. It didn't preserve it and it actually would give up on moving instructions in many cases when they were used by an LCSSA phi node. I've taught LICM to support detecting LCSSA-form PHI nodes and to hoist and sink around them. This may actually let LICM fire significantly more because we put everything into LCSSA form to rotate the loop before running LICM. =/ Now LICM should handle that fine and preserve it correctly. The down side is that LICM has to require LCSSA in order to preserve it. This is just a fact of life for LCSSA. It's entirely possible we should completely remove LCSSA from the optimizer. The test updates are essentially accomodating LCSSA phi nodes in the output of LICM, and the fact that we now completely sink every instruction in ashr-crash below the loop bodies prior to unrolling. With this change, LCSSA is computed only three times in the pass pipeline. One of them could be removed (and potentially a SCEV run and a separate LoopPassManager entirely!) if we had a LoopPass variant of InstCombine that ran InstCombine on the loop body but refused to combine away LCSSA PHI nodes. Currently, this also prevents loop unrolling from being in the same loop pass manager is rotate, LICM, and unswitch. There is one thing that I *really* don't like -- preserving LCSSA in LICM is quite expensive. We end up having to re-run LCSSA twice for some loops after LICM runs because LICM can undo LCSSA both in the current loop and the parent loop. I don't really see good solutions to this other than to completely move away from LCSSA and using tools like SSAUpdater instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200067 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an easy use of EmitRawText from PPC.Rafael Espindola2014-01-25
| | | | | | This makes lib/Target/PowerPC EmitRawText free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200065 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "Add Constant Hoisting Pass" (r200034)"Juergen Ributzka2014-01-25
| | | | | | | This reverts commit r200058 and adds the using directive for ARMTargetTransformInfo to silence two g++ overload warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200062 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix llvm-dis to print the inalloca bit on allocas.Reid Kleckner2014-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200059 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Add Constant Hoisting Pass" (r200034)Hans Wennborg2014-01-25
| | | | | | | | | | | | | | | This commit caused -Woverloaded-virtual warnings. The two new TargetTransformInfo::getIntImmCost functions were only added to the superclass, and to the X86 subclass. The other targets were not updated, and the warning highlighted this by pointing out that e.g. ARMTTI::getIntImmCost was hiding the two new getIntImmCost variants. We could pacify the warning by adding "using TargetTransformInfo::getIntImmCost" to the various subclasses, or turning it off, but I suspect that it's wrong to leave the functions unimplemnted in those targets. The default implementations return TCC_Free, which I don't think is right e.g. for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200058 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] TargetStreamer ELF flag Support for default and commandline options.Jack Carter2014-01-25
| | | | | | | | | | | | | | | | This patch uses a common MipsTargetSteamer interface for both MipsAsmPrinter and MipsAsmParser for recording default and commandline driven directives that affect ELF header flags. It has been noted that the .ll tests affected by this patch belong in test/Codegen/Mips. I will move them in a separate patch. Also, a number of directives do not get expressed by AsmPrinter in the resultant .s assembly such as setting the correct ASI. I have noted this in the tests and they will be addressed in later patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200051 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Removed unused i8 type from FPR8 register class.Ana Pazos2014-01-24
| | | | | | | | | | | | | | | | | The i8 type is not registered with any register class. This causes a segmentation fault in MachineLICM::getRegisterClassIDAndCost. The code selects the first type associated with register class FPR8, which happens to be i8. It uses this type (i8) to get the representative class pointer, which is 0. It then uses this pointer to access a field, resulting in segmentation fault. Since i8 type is not being used for printing any neon instruction we can safely remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200046 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ObjectFile ownership of the MemoryBuffer optional.Rafael Espindola2014-01-24
| | | | | | This allows llvm-ar to mmap the input files only once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200040 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Constant Hoisting PassJuergen Ributzka2014-01-24
| | | | | | | | Retry commit r200022 with a fix for the build bot errors. Constant expressions have (unlike instructions) module scope use lists and therefore may have users in different functions. The fix is to simply ignore these out-of-function uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200034 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix DAGCombiner::GatherAllAliases to account for non-chain dependenciesHal Finkel2014-01-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DAGCombiner::GatherAllAliases, which is only used when AA used is enabled during DAGCombine, had a fundamentally incorrect assumption for which this change compensates. GatherAllAliases, which is used to find aliasing predecessor chain nodes (so that a better chain can be selected for a load or store to enable subsequent optimizations) assumed that walking up the chain would always catch all possibly-aliasing loads and stores. This is not true: To really find all aliases, we also need to search for aliases through the value operand of a store, etc. Consider the following situation: Token1 = ... L1 = load Token1, %52 S1 = store Token1, L1, %51 L2 = load Token1, %52+8 S2 = store Token1, L2, %51+8 Token2 = Token(S1, S2) L3 = load Token2, %53 S3 = store Token2, L3, %52 L4 = load Token2, %53+8 S4 = store Token2, L4, %52+8 If we search for aliases of S3 (which loads address %52), and we look only through the chain, then we'll miss the trivial dependence on L1 (which loads from %52). We then might change all loads and stores to use Token1 as their chain operand, which could result in copying %53 into %52 before copying %52 into %51 (which should happen first). The problem is, however, that searching for such data dependencies can become expensive, and the cost is not directly related to the chain depth. Instead, we'll rule out such configurations by insisting that we've visited all chain users (except for users of the original chain, which is not necessary). When doing this, we need to look through nodes we don't care about (otherwise, things like register copies will interfere with trivial use cases). Unfortunately, I don't have a small test case for this problem. Creating the underlying situation is not hard (a pair of memcpys will do it), but arranging for the default instruction schedule to be incorrect is very fragile. This unbreaks self hosting on PPC64 when using -mllvm -combiner-global-alias-analysis -mllvm -combiner-alias-analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200033 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Don't try to use aggregate elements of ConstantExprs.Benjamin Kramer2014-01-24
| | | | | | PR18600. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200028 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Add Constant Hoisting Pass"Juergen Ributzka2014-01-24
| | | | | | This reverts commit r200022 to unbreak the build bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200024 91177308-0d34-0410-b5e6-96231b3b80d8
* Restrict FindBetterChain DAG combines to unindexed nodesHal Finkel2014-01-24
| | | | | | | | | | | | These transformations obviously won't work for indexed (pre/post-inc) loads and stores. In practice, I'm not sure there is any benefit to enabling them for indexed nodes because other transformations that these might enable likely also won't handle indexed nodes. I don't have an in-tree test case that hits this problem, but an upcoming bug fix will make it much more likely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Constant Hoisting PassJuergen Ributzka2014-01-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass identifies expensive constants to hoist and coalesces them to better prepare it for SelectionDAG-based code generation. This works around the limitations of the basic-block-at-a-time approach. First it scans all instructions for integer constants and calculates its cost. If the constant can be folded into the instruction (the cost is TCC_Free) or the cost is just a simple operation (TCC_BASIC), then we don't consider it expensive and leave it alone. This is the default behavior and the default implementation of getIntImmCost will always return TCC_Free. If the cost is more than TCC_BASIC, then the integer constant can't be folded into the instruction and it might be beneficial to hoist the constant. Similar constants are coalesced to reduce register pressure and materialization code. When a constant is hoisted, it is also hidden behind a bitcast to force it to be live-out of the basic block. Otherwise the constant would be just duplicated and each basic block would have its own copy in the SelectionDAG. The SelectionDAG recognizes such constants as opaque and doesn't perform certain transformations on them, which would create a new expensive constant. This optimization is only applied to integer constants in instructions and simple (this means not nested) constant cast experessions. For example: %0 = load i64* inttoptr (i64 big_constant to i64*) Reviewed by Eric git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200022 91177308-0d34-0410-b5e6-96231b3b80d8
* Add final and owerride keywords to TargetTransformInfo's subclasses.Juergen Ributzka2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200021 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix known typosAlp Toker2014-01-24
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
* InstSimplify: Make shift, select and GEP simplifications vector-aware.Benjamin Kramer2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200016 91177308-0d34-0410-b5e6-96231b3b80d8
* Unify duplicated functions.Rafael Espindola2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200014 91177308-0d34-0410-b5e6-96231b3b80d8
* Move emitInlineAsmEnd to the AsmPrinter interface.Rafael Espindola2014-01-24
| | | | | | | | There is no inline asm in a .s file. Therefore, there should be no logic to handle it in the streamer. Inline asm only exists in bitcode files, so the logic can live in the (long misnamed) AsmPrinter class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200011 91177308-0d34-0410-b5e6-96231b3b80d8
* DWARFContext: Fix possible memory leak since r198908.NAKAMURA Takumi2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200000 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Use DW_AT_high_pc and DW_AT_low_pc for the high and low pc for a"Eric Christopher2014-01-24
| | | | | | | | in order to fix the cygwin/mingw bots. This reverts commit r199990. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199991 91177308-0d34-0410-b5e6-96231b3b80d8
* Use DW_AT_high_pc and DW_AT_low_pc for the high and low pc for aEric Christopher2014-01-24
| | | | | | | | compile unit. Make these relocations on the platforms that need relocations and add a routine to ensure that we don't put the addresses in an offset table for split dwarf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199990 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.Kevin Qin2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199978 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Add support for JIT in Sparc64.Venkatraman Govindaraju2014-01-24
| | | | | | | With this change, all supported tests in test/ExecutionEngine pass in sparcv9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199977 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Prevent the creation of redundant ops for sadd and ssub with overflow.Juergen Ributzka2014-01-24
| | | | | | | | | | | | | This commit teaches the X86 backend to create the same X86 instructions when it lowers an sadd/ssub with overflow intrinsic and a conditional branch that uses that overflow result. This allows SelectionDAG to recognize and remove one of the redundant operations. This fixes <rdar://problem/15874016> and <rdar://problem/15661073>. Reviewed by Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199976 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement atomicrmw operations in 32 and 64 bits for SPARCv9.Jakob Stoklund Olesen2014-01-24
| | | | | | These all use the compare-and-swap CASA/CASXA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199975 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Correct quad register list in the asm parser.Venkatraman Govindaraju2014-01-24
| | | | | | | Add test cases to check parsing of v9 double registers and their aliased quad registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199974 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the logic for deciding when to initialize the sections.Rafael Espindola2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199971 91177308-0d34-0410-b5e6-96231b3b80d8
* Most streamers' InitSections just create a text section. Make that the defaultRafael Espindola2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199969 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the actual .text section, it is less code than building a dummy one.Rafael Espindola2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199968 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline trivial functions called only once or twice.Rafael Espindola2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199967 91177308-0d34-0410-b5e6-96231b3b80d8
* [LPM] Fix a logic error in LICM spotted by inspection.Chandler Carruth2014-01-24
| | | | | | | | | | | | We completely skipped promotion in LICM if the loop has a preheader or dedicated exits, but not *both*. We hoist if there is a preheader, and sink if there are dedicated exits, but either hoisting or sinking can move loop invariant code out of the loop! I have no idea if this has a practical consequence. If anyone has ideas for a test case, let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199966 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline functions that are only called once.Rafael Espindola2014-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199965 91177308-0d34-0410-b5e6-96231b3b80d8
* [cleanup] Use the type-based preservation method rather than a stringChandler Carruth2014-01-24
| | | | | | | literal that bakes a pass name and forces parsing it in the pass manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199963 91177308-0d34-0410-b5e6-96231b3b80d8
* InitToTextSection is redundant with InitSections. Remove it.Rafael Espindola2014-01-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199955 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the use of DW_AT_ranges in the compile unit depend also uponEric Christopher2014-01-23
| | | | | | the existence of comdat/special sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199954 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove duplicated info on what .text, .data and .bss look like.Rafael Espindola2014-01-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199951 91177308-0d34-0410-b5e6-96231b3b80d8
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