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* whitespaceAndrew Trick2013-09-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190973 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two issues regarding Got pointer (GP) setup.Reed Kotler2013-09-18
| | | | | | | | | | | | | | | | | 1) make sure that the first two instructions of the sequence cannot separate from each other. The linker requires that they be sequential. If they get separated, it can still work but it will not work in all cases because the first of the instructions mostly involves the hi part of the pc relative offset and that part changes slowly. You would have to be at the right boundary for this to matter. 2) make sure that this sequence begins on a longword boundary. There appears to be a bug in binutils which makes some of these calculations get messed up if the instruction sequence does not begin on a longword boundary. This is being investigated with the appropriate binutils folks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190966 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: Get rid of the VLA indirection hack in FastISel.Adrian Prantl2013-09-18
| | | | | | | | Use the DIVariable::isIndirect() flag set by the frontend instead of guessing whether to set the machine location's indirection bit. Paired commit with CFE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190961 91177308-0d34-0410-b5e6-96231b3b80d8
* Make DynamicLibrary use ManagedStatic. This is pretty simple and should just ↵Filip Pizlo2013-09-18
| | | | | | | | | | | | work as advertised - but it does have the caveat that calls to DynamicLibrary::AddSymbol will "reset" if you shutdown llvm and try to come back for seconds. This is a subtle behavior change, but I'm assuming that nobody is affected by it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190946 91177308-0d34-0410-b5e6-96231b3b80d8
* More XCore TTI cleanup -- remove an unused private field flagged byChandler Carruth2013-09-18
| | | | | | -Wunused-private-field with Clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190941 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] call __asan_stack_malloc_N only if use-after-return detection is ↵Kostya Serebryany2013-09-18
| | | | | | enabled with the run-time option git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190939 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/XCore/CMakeLists.txt: Add XCoreTargetTransformInfo.cpp.NAKAMURA Takumi2013-09-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190937 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent LoopVectorizer and SLPVectorizer running if the target has no vector ↵Robert Lytton2013-09-18
| | | | | | | | | | registers. XCore target: Add XCoreTargetTransformInfo This is where getNumberOfRegisters() resides, which in turn returns the number of vector registers (=0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190936 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add unsigned compare-and-branch instructionsRichard Sandiford2013-09-18
| | | | | | | | | | | | | | | | For some reason I never got around to adding these at the same time as the signed versions. No idea why. I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether it should just be replaced with an "is normal" flag. I'll leave that for later though. There are some boundary conditions that can be tweaked, such as preferring unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256", but again I'll leave those for a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190930 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-18
| | | | | | | Patch by Bradley Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r190921. It broke Windows.Filip Pizlo2013-09-18
| | | | | | | | | I'll roll it back in when I have a chance to look at it in detail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190923 91177308-0d34-0410-b5e6-96231b3b80d8
* Make DynamicLibrary use ManagedStatic. This is pretty simple and should just ↵Filip Pizlo2013-09-18
| | | | | | | | | | | | work as advertised - but it does have the caveat that calls to DynamicLibrary::AddSymbol will "reset" if you shutdown llvm and try to come back for seconds. This is a subtle behavior change, but I'm assuming that nobody is affected by it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190921 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent extra calls to ToggleFeature for Feature64Bit and FeatureCMOV if ↵Craig Topper2013-09-18
| | | | | | they've already been enabled. The extra call ends up clearing the bit in FeatureBits since its a 'toggle'. Can't prove that anything was broken because of this since I don't think the FeatureBits for these are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190920 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix X86 subtarget to not overwrite the autodetected features by calling ↵Craig Topper2013-09-18
| | | | | | InitMCProcessorInfo right after detecting them. Instead add a new function that only updates the scheduling model and call that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190919 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert accidental commit I had to make to get the test case in PR17268 to ↵Craig Topper2013-09-18
| | | | | | still work correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190917 91177308-0d34-0410-b5e6-96231b3b80d8
* Lift alignment restrictions for load/store folding on ↵Craig Topper2013-09-18
| | | | | | VINSERTF128/VEXTRACTF128. Fixes PR17268. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190916 91177308-0d34-0410-b5e6-96231b3b80d8
* ifndef NDEBUG-out an asserts-only constant committed in r190863David Blaikie2013-09-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190905 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a constant folding address space place I missed.Matt Arsenault2013-09-17
| | | | | | | | If address space 0 was smaller than the address space in a constant inttoptr/ptrtoint pair, the wrong mask size would be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190899 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Ensure that objects produced by LLVM link with /safesehReid Kleckner2013-09-17
| | | | | | | | | | | | | | | | | | | | Summary: We indicate that the object files are safe by emitting a @feat.00 absolute address symbol. The address is presumably interpreted as a bitfield of features that the compiler would like to enable. Bit 0 is documented in the PE COFF spec to opt in to "registered SEH", which is what /safeseh enables. LLVM's object files are safe by default because LLVM doesn't know how to produce SEH handlers. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190898 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the load slicing done in r190870.Quentin Colombet2013-09-17
| | | | | | | | To avoid regressions with bitfield optimizations, this slicing should take place later, like ISel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190891 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Emit all MCSymbols rather than filtering out some of themReid Kleckner2013-09-17
| | | | | | | | | | In particular, this means we emit non-external symbols defined to variables, such as aliases or absolute addresses. This is needed to implement /safeseh, and it appears there was some confusion about what symbols to emit previously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190888 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Remove ExportSection, which has been dead since r114823Reid Kleckner2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190887 91177308-0d34-0410-b5e6-96231b3b80d8
* Move variable into assert to avoid unused variable warning.Eric Christopher2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190886 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup handling of constant function casts.Matt Arsenault2013-09-17
| | | | | | | | | | Some of this code is no longer necessary since int<->ptr casts are no longer occur as of r187444. This also fixes handling vectors of pointers, and adds a bunch of new testcases for vectors and address spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190885 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add a FIXME.Bill Schmidt2013-09-17
| | | | | | | | | Documenting a design choice to generate only medium model sequences for TLS addresses at this time. Small and large code models could be supported if necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190883 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix problems with large code model (PR17169).Bill Schmidt2013-09-17
| | | | | | | | | | | | | | | Large code model on PPC64 requires creating and referencing TOC entries when using the addis/ld form of addressing. This was not being done in all cases. The changes in this patch to PPCAsmPrinter::EmitInstruction() fix this. Two test cases are also modified to reflect this requirement. Fast-isel was not creating correct code for loading floating-point constants using large code model. This also requires the addis/ld form of addressing. Previously we were using the addis/lfd shortcut which is only applicable to medium code model. One test case is modified to reflect this requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190882 91177308-0d34-0410-b5e6-96231b3b80d8
* Costmodel: Add support for horizontal vector reductionsArnold Schwaighofer2013-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upcoming SLP vectorization improvements will want to be able to estimate costs of horizontal reductions. Add infrastructure to support this. We model reductions as a series of (shufflevector,add) tuples ultimately followed by an extractelement. For example, for an add-reduction of <4 x float> we could generate the following sequence: (v0, v1, v2, v3) \ \ / / \ \ / + + (v0+v2, v1+v3, undef, undef) \ / ((v0+v2) + (v1+v3), undef, undef) %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7 %r = extractelement <4 x float> %bin.rdx8, i32 0 This commit adds a cost model interface "getReductionCost(Opcode, Ty, Pairwise)" that will allow clients to ask for the cost of such a reduction (as backends might generate more efficient code than the cost of the individual instructions summed up). This interface is excercised by the CostModel analysis pass which looks for reduction patterns like the one above - starting at extractelements - and if it sees a matching sequence will call the cost model interface. We will also support a second form of pairwise reduction that is well supported on common architectures (haddps, vpadd, faddp). (v0, v1, v2, v3) \ / \ / (v0+v1, v2+v3, undef, undef) \ / ((v0+v1)+(v2+v3), undef, undef, undef) %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef> %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef> %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1 %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx.1 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1 %r = extractelement <4 x float> %bin.rdx.1, i32 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190876 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Don't vectorize phi nodes that use invoke valuesArnold Schwaighofer2013-09-17
| | | | | | | | | We can't insert an insertelement after an invoke. We would have to split a critical edge. So when we see a phi node that uses an invoke we just give up. radar://14990770 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190871 91177308-0d34-0410-b5e6-96231b3b80d8
* [InstCombiner] Slice a big load in two loads when the elements are next to eachQuentin Colombet2013-09-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | other in memory. The motivation was to get rid of truncate and shift right instructions that get in the way of paired load or floating point load. E.g., Consider the following example: struct Complex { float real; float imm; }; When accessing a complex, llvm was generating a 64-bits load and the imm field was obtained by a trunc(lshr) sequence, resulting in poor code generation, at least for x86. The idea is to declare that two load instructions is the canonical form for loading two arithmetic type, which are next to each other in memory. Two scalar loads at a constant offset from each other are pretty easy to detect for the sorts of passes that like to mess with loads. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190870 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused code, which had been commented out.Preston Gurd2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190869 91177308-0d34-0410-b5e6-96231b3b80d8
* Added documentation to getMemsetStores.Serge Pavlov2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190866 91177308-0d34-0410-b5e6-96231b3b80d8
* Add llvm.x86.* intrinsics for Intel SHA ExtensionsBen Langmuir2013-09-17
| | | | | | | | | Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as well as tests. Also remove mayLoad and hasSideEffects, which can be inferred from the instruction patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190864 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] inline the calls to __asan_stack_free_* with small sizes. Yet another ↵Kostya Serebryany2013-09-17
| | | | | | 10%-20% speedup for use-after-return git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190863 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190862 91177308-0d34-0410-b5e6-96231b3b80d8
* Bugfix for PR17099:Stepan Dyatkovskiy2013-09-17
| | | | | | | | | | | | | Wrong cast operation. MergeFunctions emits Bitcast instead of pointer-to-integer operation. Patch fixes MergeFunctions::writeThunk function. It replaces unconditional Bitcast creation with "Value* createCast(...)" method, that checks operand types and selects proper instruction. See unit-test as example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190859 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Converted to Unix styleElena Demikhovsky2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190851 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AES and SHA instructions to the load folding tables.Craig Topper2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190850 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix column alignment. No functional change.Craig Topper2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190849 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement 3 AArch64 neon instructions : umov smov ins.Kevin Qin2013-09-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
* [SelectionDAG] Teach the vector scalarizer about TRUNCATE.Quentin Colombet2013-09-17
| | | | | | | | | | | | When a truncate node defines a legal vector type but uses an illegal vector type, the legalization process was splitting the vector until <1 x vector> type, but then it was failing to scalarize the node because it did not know how to handle TRUNCATE. <rdar://problem/14989896> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190830 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: Fix PR16736 and rdar://problem/14990587.Adrian Prantl2013-09-16
| | | | | | | A DBG_VALUE is register-indirect iff the first operand is a register _and_ the second operand is an immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190821 91177308-0d34-0410-b5e6-96231b3b80d8
* MemCpyOptimizer: Use max legal int size instead of pointer sizeMatt Arsenault2013-09-16
| | | | | | | | | | | | If there are no legal integers, assume 1 byte. This makes more sense than using the pointer size as a guess for the maximum GPR width. It is conceivable to want to use some 64-bit pointers on a target where 64-bit integers aren't legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190817 91177308-0d34-0410-b5e6-96231b3b80d8
* Use reference instead of copy.Jakub Staszak2013-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190813 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit.Bill Schmidt2013-09-16
| | | | | | | | | | Fast-isel generates a COPY_TO_REGCLASS for widening f32 to f64, which is a nop on PPC64. This is needed to keep the register class system happy, but on the fast-isel path it is not removed before emit as it is for DAG select. Ignore this op when emitting instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190795 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't vectorize if there are outside loop users of the induction variable.Arnold Schwaighofer2013-09-16
| | | | | | | | | | | | We would have to compute the pre increment value, either by computing it on every loop iteration or by splitting the edge out of the loop and inserting a computation for it there. For now, just give up vectorizing such loops. Fixes PR17179. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190790 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Check return value of main().Evgeniy Stepanov2013-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190782 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements Mips load/store instructions from/to coprocessor 2. ↵Vladimir Medic2013-09-16
| | | | | | Test cases are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Deduplicate ConstantPoolValues.Benjamin Kramer2013-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190779 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve extload handlingRichard Sandiford2013-09-16
| | | | | | | | | | | | | The port originally had special patterns for extload, mapping them to the same instructions as sextload. It seemed neater to have patterns that match "an extension that is allowed to be signed" and "an extension that is allowed to be unsigned". This was originally meant to be a clean-up, but it does improve the handling of promoted integers a little, as shown by args-06.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190777 91177308-0d34-0410-b5e6-96231b3b80d8
* Make F16C feature flag imply AVX rather than just checking both at the patterns.Craig Topper2013-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190775 91177308-0d34-0410-b5e6-96231b3b80d8
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