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* Put GCOVFile and other related interface in a common header so that llvm-cov ↵Devang Patel2011-10-04
| | | | | | tool can share it with GCOV writer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141095 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak MSVC build.Francois Pichet2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141093 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach PPCInstrInfo to handle sub-classes.Jakob Stoklund Olesen2011-10-04
| | | | | | This has already been done for most other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: add preprocessor as a separate modeChe-Liang Chiou2011-10-04
| | | | | | | | | | | | | | | | This patch adds a preprocessor that can expand nested for-loops for saving some copy-n-paste in *.td files. The preprocessor is not yet integrated with TGParser, and so it has no direct effect on *.td inputs. However, you may preprocess an td input (and only preprocess it). To test the proprecessor, type: tblgen -E -o $@ $< git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141079 91177308-0d34-0410-b5e6-96231b3b80d8
* Set operation actions to legal types only.Nadav Rotem2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141075 91177308-0d34-0410-b5e6-96231b3b80d8
* Operations should be custom lowered only if their type is legal.Nadav Rotem2011-10-04
| | | | | | | | Test: CellSPU/v2i32.ll when running with -promote-elements git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074 91177308-0d34-0410-b5e6-96231b3b80d8
* The product of two chrec's can always be represented as a chrec.Nick Lewycky2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141066 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-04
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR should avoid redundant edge splitting.Andrew Trick2011-10-04
| | | | | | | | | This handles the case in which LSR rewrites an IV user that is a phi and splits critical edges originating from a switch. Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141059 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141058 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove last references to hotpatch.Rafael Espindola2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
* Generic cleanup.Bill Wendling2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141050 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. 80 columns.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the PC label ID rather than '1'. Add support for thumb-2, because I ↵Bill Wendling2011-10-03
| | | | | | heard that some people use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't carry over the dispatchsetup hack from the old system.Bill Wendling2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141040 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in comments.Nick Lewycky2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141032 91177308-0d34-0410-b5e6-96231b3b80d8
* Check-pointing the new SjLj EH lowering.Bill Wendling2011-10-03
| | | | | | | | | | | | This code will replace the version in ARMAsmPrinter.cpp. It creates a new machine basic block, which is the dispatch for the return from a longjmp call. It then shoves the address of that machine basic block into the correct place in the function context so that the EH runtime will jump to it directly instead of having to go through a compare-and-jump-to-the-dispatch bit. This should be more efficient in the common case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit logical NOR.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit count leading ones and zeros instructions.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling2011-10-03
| | | | | | the need for returning a std::pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit divide instructions.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
* Add C api for Instruction->eraseFromParent().Devang Patel2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141023 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 ADD/SUB can take SP as a destination register.Jim Grosbach2011-10-03
| | | | | | | It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integerAkira Hatanaka2011-10-03
| | | | | | | | registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit integer multiply instructions.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of instructions which move values between 64-bit integerAkira Hatanaka2011-10-03
| | | | | | | | | registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions of the instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-03
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Eric Christopher2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Eric Christopher2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141004 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the returns_twice attribute to LLVM.Rafael Espindola2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001 91177308-0d34-0410-b5e6-96231b3b80d8
* Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to ↵Craig Topper2011-10-03
| | | | | | registers xmm8-xmm15 outside 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.Craig Topper2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140993 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r140979 with fix! We never did get a testcase, but careful review of theNick Lewycky2011-10-03
| | | | | | | logic by David Meyer revealed this bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140992 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r140979 due to reports of bootstrap failure.Nick Lewycky2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140980 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one more case we compute a max trip count.Nick Lewycky2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140979 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-02
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
* Special case disassembler handling of REX.B prefix on NOP instruction to ↵Craig Topper2011-10-02
| | | | | | decode as XCHG R8D, EAX instead. Fixes PR10344. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new icmp+select optz'n. Also shows off the load(cst) folding added inNick Lewycky2011-10-02
| | | | | | | r140966. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140969 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance a couple places where we were doing constant folding of instructions,Nick Lewycky2011-10-02
| | | | | | | but not load instructions. Noticed by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140966 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper2011-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-01
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."Chad Rosier2011-10-01
| | | | | | to appease nightly testers. Not quite there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
* Moved type construction out of the loop and added an assert on the legality ↵Nadav Rotem2011-10-01
| | | | | | of the type. Formatted lines to the 80 char limit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140952 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-01
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
* No one should be using the method directly. Assert if they do.Bill Wendling2011-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140947 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a convenience method to tell if two things are equal.Bill Wendling2011-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140946 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the ARMConstantPoolMBB class to handle the MBB values.Bill Wendling2011-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140943 91177308-0d34-0410-b5e6-96231b3b80d8
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