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* Don't use 'using std::error_code' in include/llvm.Rafael Espindola2014-06-12
| | | | | | This should make sure that most new uses use the std prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210835 91177308-0d34-0410-b5e6-96231b3b80d8
* GVN: Enable value forwarding for callocDuncan P. N. Exon Smith2014-06-12
| | | | | | | | | | | | | | | | | | | | | Enable value forwarding for loads from `calloc()` without an intervening store. This change extends GVN to handle the following case: %1 = tail call noalias i8* @calloc(i64 1, i64 4) %2 = bitcast i8* %1 to i32* ; This load is trivially constant zero %3 = load i32* %2, align 4 This is analogous to the handling for `malloc()` in the same places. `malloc()` returns `undef`; `calloc()` returns a zero value. Note that it is correct to return zero even for out of bounds GEPs since the result of such a GEP would be undefined. Patch by Philip Reames! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210828 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-12
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210827 91177308-0d34-0410-b5e6-96231b3b80d8
* Move DataLayout from the PPCTargetMachine to the subtarget.Eric Christopher2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210824 91177308-0d34-0410-b5e6-96231b3b80d8
* Move PPCFrameLowering into PPCSubtarget from PPCTargetMachine. UseEric Christopher2014-06-12
| | | | | | | | the initializeSubtargetDependencies code to obtain an initialized subtarget and migrate a couple of subtarget using functions to the .cpp file to avoid circular includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210822 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-12
| | | | | | | Recommit with fixed argument attribute checking code, which is required to bail out of all the cases we don't handle yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210815 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGen: enable mov.w/mov.t pairs with minsize for WoASaleem Abdulrasool2014-06-12
| | | | | | | | | Windows on ARM uses COFF/PE which is intrinsically position independent. For the case of 32-bit immediates, use a pair-wise relocation as otherwise we may exceed the range of operators. This fixes a code generation crash when using -Oz when targeting Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210814 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "[FastIsel][X86] Add support for lowering the first 8 floating-point ↵Juergen Ributzka2014-06-12
| | | | | | | | arguments." Reverting it because it breaks several tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210810 91177308-0d34-0410-b5e6-96231b3b80d8
* [llvm-symbolizer] Fix parsing DW_AT_ranges in Fission skeleton compile unit ↵Alexey Samsonov2014-06-12
| | | | | | | | | | | | | | | DIEs. Turns out that DW_AT_ranges_base attribute sets the offset for DW_AT_ranges values specified in the .dwo file, but not for DW_AT_ranges specified in the skeleton compile unit DIE in the main executable. This is extremely confusing, and would hopefully be fixed in DWARF-5 when it's finalized. For now this behavior makes sense, as otherwise Fission would break DWARF consumers who doesn't know anything about DW_AT_ranges_base. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210809 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r210721 as it causes breakage in internal builds (and possibly GDB).Eli Bendersky2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210807 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: stifle GCC warningSaleem Abdulrasool2014-06-12
| | | | | | | | | | lib/Target/X86/X86TargetTransformInfo.cpp: In member function ‘virtual unsigned int {anonymous}::X86TTI::getIntImmCost(unsigned int, unsigned int, const llvm::APInt&, llvm::Type*) const’: lib/Target/X86/X86TargetTransformInfo.cpp:920:60: warning: enumeral and non-enumeral type in conditional expression [enabled by default] This seems like an unhelpful warning, but there doesnt seem to be a controlling flag, so add an explicit cast to silence the warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210806 91177308-0d34-0410-b5e6-96231b3b80d8
* Trying to fix the windows build.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210805 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove system_error.h.Rafael Espindola2014-06-12
| | | | | | | This is a minimal change to remove the header. I will remove the occurrences of "using std::error_code" in a followup patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210803 91177308-0d34-0410-b5e6-96231b3b80d8
* adding re-include guards into lib/Support/reg*.hArtyom Skrobov2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210794 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove pimpl class from PassRegistry.Zachary Turner2014-06-12
| | | | | | | | | | | | | | | | | | | Since removeRegistrationListener is no longer called during static destruction, we can get rid of the pimpl in PassRegistry. This should clean up the code somewhat, increase clarity, and also allows us to put the Lock as a member of the class, instead of as a ManagedStatic. As part of this change, the PassInfo class is moved from PassSupport.h to its own file, to eliminate the otherwise circular header dependency between PassRegistry.h and PassSupport.h Reviewed by: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D4107 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210793 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, ↵Tom Stellard2014-06-12
| | | | | | | | | y)) for vectors" This reverts commit r210540, adds a testcase for the regression it caused, and marks the R600 test it was supposed to fix as XFAIL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210792 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the load/store optimization pass for Thumb-1.James Molloy2014-06-12
| | | | | | | | | Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out. Patch by Moritz Roth! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210789 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | | | | Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | Summary: These instructions are not implemented for any MIPS ISA so we only need testcases. Depends on D4110 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4111 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210786 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210784 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace llvm::error_code with std::error_code.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210783 91177308-0d34-0410-b5e6-96231b3b80d8
* This removes TODO added in http://reviews.llvm.org/D3658Dinesh Dwivedi2014-06-12
| | | | | | | | | | | | | The patch transforms ABS(NABS(X)) -> ABS(X) NABS(ABS(X)) -> NABS(X) Differential Revision: http://reviews.llvm.org/D4040 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210782 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | Summary: We haven't implemented this instruction so we only add a test case. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D4004 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210779 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] 80 col corrections that should have been in r210777.Daniel Sanders2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210778 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ↵Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210777 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | Summary: Depends on D3957 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210775 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add R_MIPS_PC19_S2Zoran Jovanovic2014-06-12
| | | | | | | Differential Revision: http://reviews.llvm.org/D3866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210773 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't import make_error_code into the llvm namespace.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210772 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | | | | | | FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210771 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add bgec and bgeuc instructionsZoran Jovanovic2014-06-12
| | | | | | | Differential Revision: http://reviews.llvm.org/D4017 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210770 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Teach how to dump the name of target node RDTSCP_DAG.Andrea Di Biagio2014-06-12
| | | | | | | | | | | When I originally added node RDTSCP_DAG (r207127) I forgot to add a string name for it in method 'getTargetNodeName'. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210769 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not ↵Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | | | | available on MIPS32r6/MIPS64r6 Summary: This patch updates both the assembler and the code generator. MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted. Depends on D3955 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3956 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210763 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210762 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit ↵Andrea Di Biagio2014-06-12
| | | | | | | | | | | | | vectors. This patch adds target combine rules to match: - [AVX] Horizontal add/sub of packed single/double precision floating point values from 256-bit vectors; - [AVX2] Horizontal add/sub of packed integer values from 256-bit vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210761 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ↵Daniel Sanders2014-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210760 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-12
| | | | | | | There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210756 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel] Add support for the stackmap intrinsic.Juergen Ributzka2014-06-12
| | | | | | This implements target-independent FastISel lowering for the stackmap intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210742 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefix generic_category with std::.Rafael Espindola2014-06-12
| | | | | | Sorry I missed these before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210740 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't put generic_category in the llvm namespace.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210737 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix verifier for GlobalAliases to avoid recursing into global initializers.Bob Wilson2014-06-12
| | | | | | | | | | | The verifier follows GlobalAlias operands so that it can detect cycles of alias definitions. It was doing this in a way that caused it to also recurse through initializers for the GlobalValue aliasees, and it would fail when an initializer refers to a global that is a declaration and not a definition. This patch causes it to stop recursing when it hits a global definition. <rdar://problem/17277451> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210734 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't import error_category into the llvm namespace.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210733 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't import error_condition into the llvm namespace.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210731 91177308-0d34-0410-b5e6-96231b3b80d8
* Used mapWindowsError. I missed these in the initial transition.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210729 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to fix the mingw build.Rafael Espindola2014-06-12
| | | | | | | * MingW needs mapWindowsError. * MingW is missing some entries in std::errc, but we don't use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210725 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not register and de-register PassRegistrationListeners duringZachary Turner2014-06-12
| | | | | | | | | | | | | | | | | construction and destruction. PassRegistrationListener is intended for use as a generic listener. In some cases, PassRegistrationListener-derived classes were being created, and automatically registered and de-registered in static constructors and destructors. Since ManagedStatics are destroyed prior to program shutdown, this leads to errors where an attempt is made to access a ManagedStatic that has already been destroyed. Reviewed by: rnk, dblaikie Differential Revision: http://reviews.llvm.org/D4106 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210724 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LoopUnrollPass to respect loop unrolling hints in metadata.Eli Bendersky2014-06-11
| | | | | | | | | | | | See http://reviews.llvm.org/D4090 for more details. The Clang change that produces this metadata was committed in r210667 Patch by Mark Heffernan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210721 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Add support for the sqrt intrinsic.Juergen Ributzka2014-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210720 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210719 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't acquire the mutex during the destructor of PassRegistry.Zachary Turner2014-06-11
| | | | | | | | | | | This destructor is run as part of static program termination, and so all ManagedStatics (including this lock) will have been destroyed by llvm_shutdown. Furthermore, if there is actually a race condition during static program termination, then we are just hiding a bug somewhere else, because other threads should not be running at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210717 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement get_magic with generic tools and inline it.Rafael Espindola2014-06-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210716 91177308-0d34-0410-b5e6-96231b3b80d8
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