summaryrefslogtreecommitdiff
path: root/lib
Commit message (Collapse)AuthorAge
* [RuntimeDyld] Fix handling of i386 PC-rel external relocations. This fixesLang Hames2014-05-13
| | | | | | | | | | several more i386 MCJIT regression test failures. <rdar://problem/16889891> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208735 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing line breaks to debug output in CodeGenPrepareLouis Gerbarg2014-05-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208731 91177308-0d34-0410-b5e6-96231b3b80d8
* GVN: Fix non-determinism in map iteration.Benjamin Kramer2014-05-13
| | | | | | | | | Iterating over a DenseMaop is non-deterministic and results to unpredictable IR output. Based on a patch by Daniel Reynaud! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208728 91177308-0d34-0410-b5e6-96231b3b80d8
* GVN: rangify a couple of loops.Benjamin Kramer2014-05-13
| | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208727 91177308-0d34-0410-b5e6-96231b3b80d8
* Save the optimization level the subtarget was created with in aEric Christopher2014-05-13
| | | | | | | | | | member variable and sink the initialization of crbits into the subtarget feature reset code. No functional change, but this refactor will be used in a future commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208726 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the split function use StringRef::split.Eric Christopher2014-05-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208723 91177308-0d34-0410-b5e6-96231b3b80d8
* Split GlobalValue into GlobalValue and GlobalObject.Rafael Espindola2014-05-13
| | | | | | | | | This allows code to statically accept a Function or a GlobalVariable, but not an alias. This is already a cleanup by itself IMHO, but the main reason for it is that it gives a lot more confidence that the refactoring to fix the design of GlobalAlias is correct. That will be a followup patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208716 91177308-0d34-0410-b5e6-96231b3b80d8
* Check explicitly for EHABI and just use the default settings.Joerg Sonnenberger2014-05-13
| | | | | | | Code depends on the assembler and linker to fix things up... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208715 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ↵Christian Pirker2014-05-13
| | | | | | | | | | | | | | file This commit was already commited as revision rL208689 and discussd in phabricator revision D3704. But the test file was crashing on OS X and windows. I fixed the test file in the same way as in rL208340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208711 91177308-0d34-0410-b5e6-96231b3b80d8
* [CGP] r205941 changed the logic, so that a cast happens *before* 'Result' isJoey Gouly2014-05-13
| | | | | | | | | | | | compared to 'AddrMode.BaseReg'. In the case that 'AddrMode.BaseReg' is nullptr, 'Result' will also be nullptr, so the cast causes an assertion. We should use dyn_cast_or_null here to check 'Result' is not null and it is an instruction. Bug found by Mats Petersson, and I reduced his IR to get a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208705 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola2014-05-13
| | | | | | | | This reverts commit r208689. The test was crashing on OS X and windows. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208704 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker2014-05-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208689 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Free up two values in SubtargetFeatureFlag by folding the redundant ↵Daniel Sanders2014-05-13
| | | | | | | | | | | | | | | | | | | | | IsGP32/IsGP64 into IsGP32bit/IsGP64bit Summary: We are currently very close to the 32-bit limit of the current assembler implementation. This is because there is no way to represent an instruction that is available in, for example, Mips3 or Mips32. We have to define a feature bit that represents this. This patch cleans up a pair of redundant feature bits and slightly postpones the point we will reach the limit. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3703 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208685 91177308-0d34-0410-b5e6-96231b3b80d8
* [un]wrap extracted from lib/Target/Target[MachineC].cpp, ↵Artyom Skrobov2014-05-13
| | | | | | lib/ExecutionEngine/ExecutionEngineBindings.cpp into include/llvm/IR/DataLayout.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208680 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg ↵Kevin Qin2014-05-13
| | | | | | | | | addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208669 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix type of shuffle resulted from shuffle merge.Serge Pavlov2014-05-13
| | | | | | | This fix resolves PR19730. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208666 91177308-0d34-0410-b5e6-96231b3b80d8
* Assert that we don't RAUW a Constant with a ConstantExpr that contains it.Rafael Espindola2014-05-13
| | | | | | | | We already had an assert for foo->RAUW(foo), but not for something like foo->RAUW(GEP(foo)) and would go in an infinite loop trying to apply the replacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208663 91177308-0d34-0410-b5e6-96231b3b80d8
* Folding into CSEL when there is ZEXT between SETCC and ADDWeiming Zhao2014-05-13
| | | | | | | | | | | | | | Normally, patterns like (add x, (setcc cc ...)) will be folded into (csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they won't be folded. This patch recognizes the ZEXT and allows the generation of CSINC. This patch fixes bug 19680. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208660 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "DebugInfo: Include lexical scopes in inlined subroutines."David Blaikie2014-05-12
| | | | | | | | | This reverts commit r208506. Some inlined subroutine scopes appear to be missing with this change. Reverting while I investigate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208642 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a logical not when inverting SetCC. This unfortunately doesn't fire on ↵Pete Cooper2014-05-12
| | | | | | | | | | | | | any targets so I couldn't find a test case to trigger it. The problem occurs when a non-i1 setcc is inverted. For example 'i8 = setcc' will get 'xor 0xff' to invert this. This is clearly wrong when the boolean contents are ZeroOrOne. This patch introduces getLogicalNOT and updates SetCC legalisation to use it. Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208641 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Split up an indexed load if only the base pointer value is liveAdam Nemet2014-05-12
| | | | | | | | | | | | | | | | | | | | Right now the load may not get DCE'd because of the side-effect of updating the base pointer. This can happen if we lower a read-modify-write of an illegal larger type (e.g. i48) such that the modification only affects one of the subparts (the lower i32 part but not the higher i16 part). See the testcase. In order to spot the dead load we need to revisit it when SimplifyDemandedBits decided that the value of the load is masked off. This is the CommitTargetLoweringOpt piece. I checked compile time with ARM64 by sending SPEC bitcode files through llc. No measurable change. Fixes <rdar://problem/16031651> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208640 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to fix an SDAG dependence issue with sretReid Kleckner2014-05-12
| | | | | | | | | | | | | | | | r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208637 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Attach DW_AT_inline to inlined subprograms at DIE-construction ↵David Blaikie2014-05-12
| | | | | | time rather than as a post-processing step. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208636 91177308-0d34-0410-b5e6-96231b3b80d8
* [RuntimeDyld] Add support for MachO __jump_table and __pointers sections, andLang Hames2014-05-12
| | | | | | | | | | | | | SECTDIFF relocations on 32-bit x86. This fixes several of the MCJIT regression test failures that show up on 32-bit builds. <rdar://problem/16886294> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208635 91177308-0d34-0410-b5e6-96231b3b80d8
* Use cast<> for unchecked useMatt Arsenault2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208627 91177308-0d34-0410-b5e6-96231b3b80d8
* use nullptr instead of NULLSebastian Pop2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208622 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support bswap16 to/from memory compiling to rev16 on ARM/ThumbLouis Gerbarg2014-05-12
| | | | | | | | | | | The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208620 91177308-0d34-0410-b5e6-96231b3b80d8
* Use cast<> for unchecked useMatt Arsenault2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208618 91177308-0d34-0410-b5e6-96231b3b80d8
* Use range forMatt Arsenault2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208617 91177308-0d34-0410-b5e6-96231b3b80d8
* do not assert when delinearization failsSebastian Pop2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208615 91177308-0d34-0410-b5e6-96231b3b80d8
* use isZero()Sebastian Pop2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208614 91177308-0d34-0410-b5e6-96231b3b80d8
* DwarfDebug: Avoid an extra map lookup while constructing abstract scope DIEs ↵David Blaikie2014-05-12
| | | | | | | | | | and reduce nesting/conditionals. One test case had to be updated as it still had the extra indirection for the variable list - removing the extra indirection got it back to passing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208608 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.Tim Northover2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208606 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.Tim Northover2014-05-12
| | | | | | | | This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208605 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SimplifyDemandedBits understand BUILD_PAIRMatt Arsenault2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208598 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert: r208582 - [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-12
| | | | | | | | Accidentally committed an unreviewed patch. Reverted it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208583 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-12
| | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: jkolek, vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D3670 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208582 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add d?div, d?mod, d?divu, d?moduDaniel Sanders2014-05-12
| | | | | | | | | | | | Summary: Depends on D3668 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208579 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Added mul/mulu/muh/muhuDaniel Sanders2014-05-12
| | | | | | | | | | | | Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3668 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208576 91177308-0d34-0410-b5e6-96231b3b80d8
* Move EmitDwarfAdvanceLineAddr and EmitDwarfAdvanceFrameAddr to the obj streamer.Rafael Espindola2014-05-12
| | | | | | This lets us delete the MCAsmStreamer implementation. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208570 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass a MCObjectStreamer instead of a MCStreamer when possible.Rafael Espindola2014-05-12
| | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208569 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass a MCObjectStreamer instead of a MCStreamer when possible.Rafael Espindola2014-05-12
| | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208567 91177308-0d34-0410-b5e6-96231b3b80d8
* Silencing an MSVC warning about not all control paths returning a value ↵Aaron Ballman2014-05-12
| | | | | | (even though the switch is fully covered). No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208565 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: remove dead validation code from the AsmParser.Tim Northover2014-05-12
| | | | | | | If this code triggers, any immediate has already been validated so it can't possibly trigger a diagnostic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208564 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-12
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208563 91177308-0d34-0410-b5e6-96231b3b80d8
* Move EH/Debug frame handling to the object streamer.Rafael Espindola2014-05-12
| | | | | | | Now that the asm streamer doesn't use it, the MCStreamer doesn't need to know about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208562 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove always true argument and unused field.Rafael Espindola2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208561 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 06:28:30 +0000