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path: root/test/CodeGen/ARM/str_pre-2.ll
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* Fix test that depends on register allocation.Jakob Stoklund Olesen2012-06-11
| | | | | | | The test is really checking the prolog/epilog load/store multiple formation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158328 91177308-0d34-0410-b5e6-96231b3b80d8
* Linear scan is going away.Jakob Stoklund Olesen2011-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144472 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-11
| | | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-11
| | | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM tests to be register allocator independent.Jakob Stoklund Olesen2011-03-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128680 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the testAnton Korobeynikov2011-01-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122666 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM stm/ldm instructions require more than one register in the register list.Jim Grosbach2010-12-09
| | | | | | | | Otherwise, a plain str/ldr should be used instead. Make sure we account for that in prologue/epilogue code generation. rdar://8745460 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121391 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite stack callee saved spills and restores to use push/pop instructions.Eric Christopher2010-11-18
| | | | | | | | | | Remove movePastCSLoadStoreOps and associated code for simple pointer increments. Update routines that depended upon other opcodes for save/restore. Adjust all testcases accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119725 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck'izeJim Grosbach2010-10-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117401 91177308-0d34-0410-b5e6-96231b3b80d8
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-17
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-16
| | | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 72756 with fixes. One of those was introduced by we changed ↵Evan Cheng2009-06-04
| | | | | | MachineInstrBuilder::addReg() interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert 72756 for now.Evan Cheng2009-06-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold preceding / trailing base inc / dec into the single load / store as well.Evan Cheng2009-06-03
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
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