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* Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.Kalle Raiskila2011-09-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8
* make the asmparser reject function and type redefinitions. 'Merging' hasn't ↵Chris Lattner2011-06-17
| | | | | | | | | been needed since llvm-gcc 3.4 days. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133248 91177308-0d34-0410-b5e6-96231b3b80d8
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-17
| | | | | | | | are either unreduced or only test old syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133228 91177308-0d34-0410-b5e6-96231b3b80d8
* don't test for codegen of 'store undef'Chris Lattner2011-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129184 91177308-0d34-0410-b5e6-96231b3b80d8
* Roll r127459 back in:Cameron Zwarich2011-03-11
| | | | | | | | | | | Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often getDaniel Dunbar2011-03-11
| | | | | | created from the", it broke some GCC test suite tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize trivial branches in CodeGenPrepare, which often get created from theCameron Zwarich2011-03-11
| | | | | | | | | | lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix mistyped CHECK lines.Benjamin Kramer2011-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127366 91177308-0d34-0410-b5e6-96231b3b80d8
* Be nice to Xcore and the XMOS assembler and avoid quoting section namesJoerg Sonnenberger2011-03-04
| | | | | | | that contain only letters, digits and the characters "_" and ".". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow vector shifts (shl,lshr,ashr) on SPU.Kalle Raiskila2011-03-04
| | | | | | | | | | | There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow load from constant on SPU.Kalle Raiskila2011-03-04
| | | | | | | A 'load <4 x i32>* null' crashes llc before this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
* Bug#9033: For the ELF assembler output, always quote the section name.Joerg Sonnenberger2011-03-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
* fix visitShift to properly zero extend the shift amount if the provided operandChris Lattner2011-02-13
| | | | | | | | is narrower than the shift register. Doing an anyext provides undefined bits in the top part of the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125457 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123912 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash SPU BE with memory accesses with big alignmnet.Kalle Raiskila2011-01-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123620 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't feed 19 bit immediates to ILA.Kalle Raiskila2010-12-17
| | | | | | | Patch (slightly modified) by Visa Putkinen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122052 91177308-0d34-0410-b5e6-96231b3b80d8
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-06
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121059 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle lshr for i128 correctly on SPU also when Kalle Raiskila2010-11-29
| | | | | | | shiftamount > 7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120288 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable PostRA scheduling for SPU. Kalle Raiskila2010-11-29
| | | | | | | | This speeds up selected test cases with up to 5% - no slowdowns observed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120286 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow for 'fcmp ogt' in SPU.Kalle Raiskila2010-11-24
| | | | | | | Fix by Visa Putkinen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120090 91177308-0d34-0410-b5e6-96231b3b80d8
* Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila2010-11-23
| | | | | | | shifts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120022 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug with extractelement on SPU.Kalle Raiskila2010-11-22
| | | | | | | | In the attached testcase, the element was never extracted (missing rotate). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119973 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix memory access lowering on SPU, addingKalle Raiskila2010-11-12
| | | | | | | | | | | | | support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
* Change v64 datalayout in SPU.Kalle Raiskila2010-10-26
| | | | | | | | | | | | | | | The SPU ABI does not mention v64, and all examples in C suggest v128 are treated similarily to arrays, we use array alignment for v64 too. This makes the alignment of e.g. [2 x <2 x i32>] behave "intuitively" and similar to as if the elements were e.g. i32s. This also makes an "unaligned store" test to be aligned, with different (but functionally equivalent) code generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117360 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-18
| | | | | | | | | The old algorithm inserted a 'rotqmbyi' instruction which was both redundant and wrong - it made shufb select bytes from the wrong end of the input quad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116701 91177308-0d34-0410-b5e6-96231b3b80d8
* Zap some redundant 'ori $?, $?, 0' from SPU.Kalle Raiskila2010-10-01
| | | | | | | | Also remove some code that died in the process. One now non-existant ori is checked for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115306 91177308-0d34-0410-b5e6-96231b3b80d8
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-16
| | | | | | | | | | | | | | This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-08
| | | | | | | Some cases of lowering to rotate were miscompiled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-29
| | | | | | | The IDX was treated as byte index, not element index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-24
| | | | | | | llc used to assert on the added testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-18
| | | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-18
| | | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
* Change SPU C calling convention to match that described in Kalle Raiskila2010-08-18
| | | | | | | | | "SPU Application Binary Interface Specification, v1.9" by IBM. Specifically: use r3-r74 to pass parameters and the return value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111358 91177308-0d34-0410-b5e6-96231b3b80d8
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-04
| | | | | | | store for "half vectors" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110198 91177308-0d34-0410-b5e6-96231b3b80d8
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110038 91177308-0d34-0410-b5e6-96231b3b80d8
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-02
| | | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110037 91177308-0d34-0410-b5e6-96231b3b80d8
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-02
| | | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110035 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-16
| | | | | | TII::isMoveInstr is going tobe completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108507 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some tests that didn't test anything.Benjamin Kramer2010-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106954 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the check to the testcase of r106419.Kalle Raiskila2010-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106421 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the SPU 'lr' instruction to never have side effects. Kalle Raiskila2010-06-21
| | | | | | | | | | This allows the fast regiser allocator to remove redundant register moves. Update a set of tests that depend on the register allocator to be linear scan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.Kalle Raiskila2010-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106419 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithmKalle Raiskila2010-06-21
| | | | | | | | used to choke llc with the attached test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106411 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SPU to cope with vector insertelement to an undef position.Kalle Raiskila2010-06-09
| | | | | | | We default to inserting to lane 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105722 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle loading from/storing to undef pointers on SPU by inserting a Kalle Raiskila2010-06-09
| | | | | | | random load/store, rather than crashing llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105710 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of 'load' nodes.Kalle Raiskila2010-06-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SPU backend not assert on jump tables.Kalle Raiskila2010-05-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of 'sf' and 'sfh' instructions.Kalle Raiskila2010-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
* "on the rare occasion the SPU BE produces illegal assembly - it tries to ↵Chris Lattner2010-05-04
| | | | | | | | | | emit an add instruction of the form 'a reg, reg, imm'." Patch by Kalle Raiskila! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103021 91177308-0d34-0410-b5e6-96231b3b80d8
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