| Commit message (Collapse) | Author | Age |
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Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
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derived class MipsSETargetLowering.
We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140872 91177308-0d34-0410-b5e6-96231b3b80d8
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Generate code for Mips32r1 unless a Mips32r2 feature is tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123760 91177308-0d34-0410-b5e6-96231b3b80d8
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