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* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-15
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add testcase for problem I ran intoMatt Arsenault2013-11-14
| | | | | | with the older version of the moveToVALU changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194682 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-13
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-13
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194547 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-12
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add test that fails due to requiring i64 mul for pointersMatt Arsenault2013-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194433 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix LowerUDIVREMVincent Lejeune2013-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CodeGen for unaligned loads with address spacesMatt Arsenault2013-10-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193721 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Custom lower f32 = uint_to_fp i64Tom Stellard2013-10-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193701 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-29
| | | | | | | | | v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193621 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector FSQRT opsTom Stellard2013-10-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193620 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: fix MIMG writemask adjustementTom Stellard2013-10-23
| | | | | | | | | | | | | This fixes piglit: - shaders/glsl-fs-texture2d-masked - shaders/glsl-fs-texture2d-masked-4 Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193222 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-23
| | | | | | | | | | The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for i64 bitwise orTom Stellard2013-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193213 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193212 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Simplify handling of private address spaceTom Stellard2013-10-22
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CodeGen for vectors of pointers with address spaces.Matt Arsenault2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193112 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CodeGen for different size address space GEPsMatt Arsenault2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193111 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix a crash in the AMDILCFGStructurizerTom Stellard2013-10-16
| | | | | | | | | | | We were calling llvm_unreachable() when failing to optimize the branch into if case. However, it is still possible for us to structurize the CFG by duplicating blocks even if this optimization fails. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192813 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192557 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: fix swizzle exportVincent Lejeune2013-10-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192553 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add scalar i32 add testMatt Arsenault2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192501 91177308-0d34-0410-b5e6-96231b3b80d8
* Use CHECK-LABELMatt Arsenault2013-10-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192500 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192375 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-10
| | | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some xfaild R600 tests.Matt Arsenault2013-10-08
| | | | | | These are bugs to fix later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192212 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Put PRED_X instruction in its own clauseVincent Lejeune2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191789 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: update tbaa format from scalar format to struct-path aware format.Manman Ren2013-09-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191690 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases when they are not needed.Manman Ren2013-09-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191689 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-28
| | | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190644 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-12
| | | | | | | This move makes possible to correctly handle multiples instructions from a single pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190643 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-12
| | | | | | | | | | | | | | For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190575 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for LDS atomic subtractAaron Watry2013-09-06
| | | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach CodeGenPrepare about address spacesMatt Arsenault2013-09-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190112 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190091 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add support for local memory atomic addTom Stellard2013-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190079 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-05
| | | | | | | GlobalAdderss nodes that appeared in more than one basic block were being counted twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190078 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190077 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189981 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove fmul.v4f32.ll test which is redundant with fmul.llVincent Lejeune2013-09-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189978 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Enable local-memory-two-objects lit testMichel Danzer2013-08-27
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189334 91177308-0d34-0410-b5e6-96231b3b80d8
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