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* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-31
| | | | | | | | | | | | | | | | | | | Unlike most -- hopefully "all other", but I'm still checking -- memory instructions we support, LOAD REVERSED and STORE REVERSED may access the memory location several times. This means that they are not suitable for volatile loads and stores. This patch is a prerequisite for better atomic load and store support. The same principle applies there: almost all memory instructions we support are inherently atomic ("block concurrent"), but LOAD REVERSED and STORE REVERSED are exceptions. Other instructions continue to allow volatile operands. I will add positive "allows volatile" tests at the same time as the "allows atomic load or store" tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183002 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-30
| | | | | | | | The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182920 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Two tests missing from previous commitRichard Sandiford2013-05-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182847 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-29
| | | | | | | This patch adds support for the CIJ and CGIJ instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182846 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-28
| | | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Tighten branch testsRichard Sandiford2013-05-21
| | | | | | | After r182274, the branches in these tests must always be short. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182358 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add long branch passRichard Sandiford2013-05-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change, the SystemZ backend would use BRCL for all branches and only consider shortening them to BRC when generating an object file. E.g. a branch on equal would use the JGE alias of BRCL in assembly output, but might be shortened to the JE alias of BRC in ELF output. This was a useful first step, but it had two problems: (1) The z assembler isn't traditionally supposed to perform branch shortening or branch relaxation. We followed this rule by not relaxing branches in assembler input, but that meant that generating assembly code and then assembling it would not produce the same result as going directly to object code; the former would give long branches everywhere, whereas the latter would use short branches where possible. (2) Other useful branches, like COMPARE AND BRANCH, do not have long forms. We would need to do something else before supporting them. (Although COMPARE AND BRANCH does not change the condition codes, the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction during codegen, so that we can safely lower it to a separate compare and long branch where necessary. This is not a valid transformation for the assembler proper to make.) This patch therefore moves branch relaxation to a pre-emit pass. For now, calls are still shortened from BRASL to BRAS by the assembler, although this too is not really the traditional behaviour. The first test takes about 1.5s to run, and there are likely to be more tests in this vein once further branch types are added. The feeling on IRC was that 1.5s is a bit much for a single test, so I've restricted it to SystemZ hosts for now. The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests. A later patch will remove the {{g}}s from that directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-15
| | | | | | | Thanks to Ulrich Weigand for noticing that this instruction was missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add CodeGen test casesUlrich Weigand2013-05-06
| | | | | | | | | | | | | This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the SystemZ backend.Dan Gohman2011-10-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-17
| | | | | | | | are either unreduced or only test old syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133228 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove custom allocation orders in SystemZ.Jakob Stoklund Olesen2011-06-15
| | | | | | | | | | | | | | | | | | Note that this actually changes code generation, and someone who understands this target better should check the changes. - R12Q is now allocatable. I think it was omitted from the allocation order by mistake since it isn't reserved. It as apparently used as a GOT pointer sometimes, and it should probably be reserved if that is the case. - The GR64 registers are allocated in a different order now. The register allocator will automatically put the CSRs last. There were other changes to the order that may have been significant. The test fix is because r0 and r1 swapped places in the allocation order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133067 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SystemZ testsJakob Stoklund Olesen2011-03-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128686 91177308-0d34-0410-b5e6-96231b3b80d8
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG ↵Devang Patel2010-12-06
| | | | | | message instead of creating DBG_VALUE for undefined value in reg0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121059 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct bogus module triple specifications.Duncan Sands2010-08-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112469 91177308-0d34-0410-b5e6-96231b3b80d8
* SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead andBill Wendling2010-05-14
| | | | | | | | | replace the check with the appropriate predicate. Modify the testcase to reflect the correct code. (It should be saving callee-saved registers on the stack allocated by the calling fuction.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103829 91177308-0d34-0410-b5e6-96231b3b80d8
* add newlines at the end of files.Chris Lattner2010-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100705 91177308-0d34-0410-b5e6-96231b3b80d8
* Split big test into multiple directories to cater toDale Johannesen2010-04-07
| | | | | | | | those who don't build all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach dag combine to fold the following transformation more aggressively:Evan Cheng2010-01-06
| | | | | | | | | | | (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92849 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix invalid chain folding for memory variant of sdiv / udivAnton Korobeynikov2010-01-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92472 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing RUN lineAnton Korobeynikov2009-08-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79707 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce the testAnton Korobeynikov2009-08-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79703 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fcopysign instructionsAnton Korobeynikov2009-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79664 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle 'r' inline asm constraintAnton Korobeynikov2009-08-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79648 91177308-0d34-0410-b5e6-96231b3b80d8
* Various AsmWriter output cleanups. Use WriteAsOperand instead ofDan Gohman2009-08-13
| | | | | | | PrintUnmangledNameSafely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78878 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcases for reg-mem arithemtics added recentlyAnton Korobeynikov2009-08-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78214 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert bswap test to filecheck, add more test entries & convert stuff to ↵Anton Korobeynikov2009-08-05
| | | | | | filecheck git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78212 91177308-0d34-0410-b5e6-96231b3b80d8
* convert this test to filecheck format, which is faster and avoids false ↵Chris Lattner2009-07-21
| | | | | | matches of "st" -> "stdin" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76591 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable cross register class coalescing.Evan Cheng2009-07-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76281 91177308-0d34-0410-b5e6-96231b3b80d8
* Make xfail properAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76065 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporary disable 16 bit bswapAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76063 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bswap patternsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76061 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix logic inversion for RI-mode address selectionAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak the testAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76051 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand 32-bit bitconverts via memoryAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76050 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incomin arg stack frame offset in case we need to generate stack frameAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76049 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the commit, it just hides the real bugAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76045 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension ↵Anton Korobeynikov2009-07-16
| | | | | | side effects git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76035 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide consistent subreg idx scheme. This (hopefully) fixes remaining ↵Anton Korobeynikov2009-07-16
| | | | | | divide problems git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement 'large' PIC modelAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76006 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement shifts properly (hopefilly - finally!)Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly handle divides. As a bonus - implement memory versions of them.Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
* 32 bit shifts have only 12 bit displacementsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8
* Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.Anton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 12 bit displacementsAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit proper lowering of load from arg stack slotAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75986 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement dynamic allocasAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75985 91177308-0d34-0410-b5e6-96231b3b80d8
* Add jump tablesAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75984 91177308-0d34-0410-b5e6-96231b3b80d8
* Add rotatesAnton Korobeynikov2009-07-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75981 91177308-0d34-0410-b5e6-96231b3b80d8
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