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* Linear scan is going away.Jakob Stoklund Olesen2011-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144472 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch ARM to using AltOrders instead of MethodBodies.Jakob Stoklund Olesen2011-06-18
| | | | | | | | | | This slightly changes the GPR allocation order on Darwin where R9 is not a callee-saved register: Before: %R0 %R1 %R2 %R3 %R12 %R9 %LR %R4 %R5 %R6 %R8 %R10 %R11 After: %R0 %R1 %R2 %R3 %R9 %R12 %LR %R4 %R5 %R6 %R8 %R10 %R11 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133326 91177308-0d34-0410-b5e6-96231b3b80d8
* fix two completely broken tests, which were matching due to PR9629.Chris Lattner2011-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129195 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Thumb and Thumb2 tests to be register allocator independent.Jakob Stoklund Olesen2011-03-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128690 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that register allocation properly considers reserved regs, simplify theJim Grosbach2010-09-02
| | | | | | | ARM register class allocation order functions to take advantage of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the first have of the optimization which eliminates BRCONDDan Gohman2010-06-24
| | | | | | | | | | | | | | when the condition is constant. This optimization shouldn't be necessary, because codegen shouldn't be able to find dead control paths that the IR-level optimizer can't find. And it's undesirable, because it encourages bugpoint to leave "br i1 false" branches in its output. And it wasn't updating the CFG. I updated all the tests I could, but some tests are too reduced and I wasn't able to meaningfully preserve them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106748 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola2010-06-17
| | | | | | matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-17
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-16
| | | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
* LowerCall() should always do getCopyFromReg() to reference the stack pointer.Jim Grosbach2010-02-24
| | | | | | | Machine instruction selection is much happier when operands are in virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
* Remat VLDRD from constpool. Clean up some instruction property specifications.Evan Cheng2009-11-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.Evan Cheng2009-11-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89326 91177308-0d34-0410-b5e6-96231b3b80d8
* Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.Evan Cheng2009-11-01
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
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