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	Commit message (Collapse)	Author	Age
*	More rewrites of x86 codegen regression tests with FileCheck	Michael Liao	2013-05-01
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180837 91177308-0d34-0410-b5e6-96231b3b80d8
*	Eliminate more uses of llvm-as and llvm-dis.	Dan Gohman	2009-09-08
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*	Split the Add, Sub, and Mul instruction opcodes into separate	Dan Gohman	2009-06-04
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
*	The coalescer does not coalesce a virtual register to a physical register if ↵	Evan Cheng	2009-01-07
	any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: v1024 = EDI // not killed = = EDI One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead. This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61847 91177308-0d34-0410-b5e6-96231b3b80d8