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* Enable MI Sched for x86.Andrew Trick2013-10-15
| | | | | | | | | | | | | | | | | | | | | | | | | | This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace more uses of sse41 with sse4.1.Rafael Espindola2013-08-23
| | | | | | | llc using the host cpu features and *waning* on unknown features is probably not a good thing :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189144 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Temporarily enable MI-Sched on X86."Andrew Trick2013-06-25
| | | | | | This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily enable MI-Sched on X86.Andrew Trick2013-06-24
| | | | | | | Sorry for the unit test churn. I'll try to make the change permanently next time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove -join-physregs from the test suite.Jakob Stoklund Olesen2012-05-17
| | | | | | | | | | | | | | This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157027 91177308-0d34-0410-b5e6-96231b3b80d8
* Add mcpu to tests to prevent them from using AVX instructions on Sandy ↵Craig Topper2012-04-27
| | | | | | Bridge after r155618. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155696 91177308-0d34-0410-b5e6-96231b3b80d8
* Prepare remaining tests for -join-physreg going away.Jakob Stoklund Olesen2011-05-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130893 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the pmulld intrinsic and autoupdate it as a vector multiply.Eric Christopher2010-03-30
| | | | | | | | Rewrite the pmulld patterns, and make sure that they fold in loads of arguments into the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99910 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use special heuristics for nodes with no data predecessorsDan Gohman2009-02-11
| | | | | | | | unless they actually have data successors, and likewise for nodes with no data successors unless they actually have data precessors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64327 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach 2addr pass to be do more commuting. If both uses of a two-address ↵Evan Cheng2009-01-25
| | | | | | | | | | | | | | | | | | | | | | instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue. %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 %reg1029<def> = MOV8rr %reg1028 %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> insert => %reg1030<def> = MOV8rr %reg1028 %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> In this case, it might not be possible to coalesce the second MOV8rr instruction if the first one is coalesced. So it would be profitable to commute it: %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 %reg1029<def> = MOV8rr %reg1028 %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> insert => %reg1030<def> = MOV8rr %reg1029 %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test to account for generating some vector code for mul v2i64 insteadMon P Wang2008-12-18
| | | | | | | of incorrectly generating pmuldq git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61228 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test independent of the target-triple; the stack alignmentDan Gohman2008-05-27
| | | | | | | is specifically what this test depends on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51599 91177308-0d34-0410-b5e6-96231b3b80d8
* The Linux ABI emits an extra "movl %esp, %ebp" in function prologue andNick Lewycky2008-05-26
| | | | | | | | | | sometimes a "mov %ebp, %esp" in the epilogue. Force these tests that rely on counting 'mov' to use i686-apple-darwin8.8.0 where they were written. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51568 91177308-0d34-0410-b5e6-96231b3b80d8
* Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And addDan Gohman2008-05-23
load-folding table entries for PMULDQ and PMULLD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
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