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* llvm.experimental.stackmap: fix encoding of large constants.Andrew Trick2014-01-09
| | | | | | | | | | In the stackmap format we advertise the constant field as signed. However, we were determining whether to promote to a 64-bit constant pool based on an unsigned comparison. This fix allows -1 to be encoded as a small constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198816 91177308-0d34-0410-b5e6-96231b3b80d8
* Conservatively handle multiple MMOs in MIsNeedChainEdgeHal Finkel2014-01-08
| | | | | | | | | | | | | | | | | | | | | | MIsNeedChainEdge, which is used by -enable-aa-sched-mi (AA in misched), had an llvm_unreachable when -enable-aa-sched-mi is enabled and we reach an instruction with multiple MMOs. Instead, return a conservative answer. This allows testing -enable-aa-sched-mi on x86. Also, this moves the check above the isUnsafeMemoryObject checks. isUnsafeMemoryObject is currently correct only for instructions with one MMO (as noted in the comment in isUnsafeMemoryObject): // We purposefully do no check for hasOneMemOperand() here // in hope to trigger an assert downstream in order to // finish implementation. The problem with this is that, had the candidate edge passed the "!MIa->mayStore() && !MIb->mayStore()" check, the hoped-for assert would never happen (which could, in theory, lead to incorrect behavior if one of these secondary MMOs was volatile, for example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198795 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the DAGCombiner how to fold 'vselect' dag nodes accordingAndrea Di Biagio2014-01-08
| | | | | | | | | | to the following two rules: 1) fold (vselect (build_vector AllOnes), A, B) -> A 2) fold (vselect (build_vector AllZeros), A, B) -> B git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198777 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Disambiguate RET[QL] and fix aliases for 16-bit modeDavid Woodhouse2014-01-08
| | | | | | | | | | I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198756 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq.Elena Demikhovsky2014-01-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198745 91177308-0d34-0410-b5e6-96231b3b80d8
* [patch] Adjust behavior of FDE cross-section relocs for targets that don't ↵Iain Sandoe2014-01-08
| | | | | | | | | | | | | | support abs-differences. Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs. This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff". At present, this is only enabled for modern x86 OSX ports. test changes by David Fang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198744 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix generating incorrect value type of NEON_VDUPLANEKevin Qin2014-01-08
| | | | | | | when lower build_vector if result value type mismatch with operand value type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198743 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assert with private type info variables.Rafael Espindola2014-01-07
| | | | | | | With the gnu objc runtime private strings are used. Since we only need to produce a unique label, the fix is to just drop the asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198701 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. ↵Hao Liu2014-01-07
| | | | | | There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198684 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q ↵Hao Liu2014-01-07
| | | | | | tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198682 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18396: Assertion: MO->isDead "Cannot fold physreg def".Andrew Trick2014-01-07
| | | | | | InlineSpiller::foldMemoryOperand needs to handle undef call operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198679 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fixed incorrect immediate used in BIC instruction.Kevin Qin2014-01-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198675 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM IAS: improve .eabi_attribute handlingSaleem Abdulrasool2014-01-07
| | | | | | | | Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198662 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-06
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198617 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore Target: correct callee save register spilling when callsUnwindInit is ↵Robert Lytton2014-01-06
| | | | | | true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198616 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Lower EH_RETURNRobert Lytton2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198615 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Lower FRAME_TO_ARGS_OFFSETRobert Lytton2014-01-06
| | | | | | | | | This requires a knowledge of the stack size which is not known until the frame is complete, hence the need for the XCoreFTAOElim pass which lowers the XCoreISD::FRAME_TO_ARGS_OFFSET instrution into its final form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198614 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Lower RETURNADDRRobert Lytton2014-01-06
| | | | | | Only handles a depth of zero (the same as FRAMEADDR) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198613 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Optimise entsp / retsp selectionRobert Lytton2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198612 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix handling of unsized global arrays in large code modelRobert Lytton2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198609 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: keep special non-AEABIness of "-darwin-eabi" triples for nowTim Northover2014-01-06
| | | | | | | | | | Longer term, we want to move users to "*-*-*-macho" for embedded work, but for now people are relying on the last thing we told them, which is unfortunately "*-*-darwin-eabi". rdar://problem/15703934 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198602 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without)Elena Demikhovsky2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198593 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Fix invalid constant used in vselect condition.Kevin Qin2014-01-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a wrong assumption that the vector element type and the type of each ConstantSDNode in the build_vector were the same. However, when promoting the integer operand of a legally typed build_vector, the operand type and the vector element type do not need to be the same (See method 'DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR' in LegalizeIntegerTypes.cpp). in AArch64 backend, the following dag sequence: C0: i1 = Constant<0> C1: i1 = Constant<-1> V: v8i1 = BUILD_VECTOR C1, C1, C0, C0, C0, C0, C0, C0 is type-legalized into: NewC0: i32 = Constant<0> NewC1: i32 = Constant<1> V: v8i8 = BUILD_VECTOR NewC1, NewC1, NewC0, NewC0, NewC0, NewC0, NewC0, NewC0 Forcing a getZeroExtend to VTBits to ensure that the new constant is correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198582 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a failing test to get the buildbots back to green.Bill Wendling2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198578 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to fix s390x build bot.Bill Wendling2014-01-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198577 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: changed property name from "neverHasSideEffects=1" to ↵Elena Demikhovsky2014-01-05
| | | | | | | | | "hasSideEffects=0", added this property to VMOVSS/VMOVSD; Optimized a truncate pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198562 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more intrinsics for convert and min/max.Elena Demikhovsky2014-01-05
| | | | | | | Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198557 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to fix buildbots by XFAILing some architectures.Bill Wendling2014-01-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198537 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit an error message if the value passed to __builtin_returnaddress isn't a ↵Bill Wendling2014-01-05
| | | | | | | | | | constant __builtin_returnaddress requires that the value passed into is be a constant. However, at -O0 even a constant expression may not be converted to a constant. Emit an error message intead of crashing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198531 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64. Venkatraman Govindaraju2014-01-04
| | | | | | | Fixes PR18356. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198480 91177308-0d34-0410-b5e6-96231b3b80d8
* [RegAlloc] Make tryInstructionSplit less aggressive.Quentin Colombet2014-01-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The greedy register allocator tries to split a live-range around each instruction where it is used or defined to relax the constraints on the entire live-range (this is a last chance split before falling back to spill). The goal is to have a big live-range that is unconstrained (i.e., that can use the largest legal register class) and several small local live-range that carry the constraints implied by each instruction. E.g., Let csti be the constraints on operation i. V1= op1 V1(cst1) op2 V1(cst2) V1 live-range is constrained on the intersection of cst1 and cst2. tryInstructionSplit relaxes those constraints by aggressively splitting each def/use point: V1= V2 = V1 V3 = V2 op1 V3(cst1) V4 = V2 op2 V4(cst2) Because of how the coalescer infrastructure works, each new variable (V3, V4) that is alive at the same time as V1 (or its copy, here V2) interfere with V1. Thus, we end up with an uncoalescable copy for each split point. To make tryInstructionSplit less aggressive, we check if the split point actually relaxes the constraints on the whole live-range. If it does not, we do not insert it. Indeed, it will not help the global allocation problem: - V1 will have the same constraints. - V1 will have the same interference + possibly the newly added split variable VS. - VS will produce an uncoalesceable copy if alive at the same time as V1. <rdar://problem/15570057> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198369 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the ARM ABI selectable via SubtargetFeature.Rafael Espindola2014-01-02
| | | | | | | This patch makes it possible to select the ABI with -mattr. It will be used to forward clang's -target-abi option to llvm's CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198304 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Handle atomic loads/stores in sparc backend.Venkatraman Govindaraju2014-01-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198286 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to ↵Venkatraman Govindaraju2014-01-01
| | | | | | __multi3() in correct order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198281 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL ↵Venkatraman Govindaraju2014-01-01
| | | | | | does not clear top 32 bit, only SRL does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198280 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmpElena Demikhovsky2014-01-01
| | | | | | | | Printing rounding control. Enncoding for EVEX_RC (rounding control). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198277 91177308-0d34-0410-b5e6-96231b3b80d8
* For AArch64 Neon, simplify scalar dup by lane0 for fp.Jiangning Liu2013-12-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198194 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad.Hao Liu2013-12-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198193 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Can't select shift left 0 of type v1i64Hao Liu2013-12-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198192 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in DAGcombiner about zero-extend after setcc.Kevin Qin2013-12-30
| | | | | | | | | | For AArch64 backend, if DAGCombiner see "sext(setcc)", it will combine them together to a single setcc with extended value type. Then if it see "zext(setcc)", it assumes setcc is Vxi1, and try to create "(and (vsetcc), (1, 1, ...)". While setcc isn't Vxi1, DAGcombiner will create wrong node and get wrong code emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198190 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64]Fix the problem that can't select mul of v1i64/v2i64 types.Hao Liu2013-12-30
| | | | | | | | E.g. Can't select such IR: %tmp = mul <2 x i64> %a, %b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198188 91177308-0d34-0410-b5e6-96231b3b80d8
* Un-XFAILify some tests which are now passing.Bill Wendling2013-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198184 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-29
| | | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198157 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] For codegen generated library calls that return float, set inreg ↵Venkatraman Govindaraju2013-12-29
| | | | | | | | | flag manually in LowerCall(). This makes the sparc backend to generate Sparc64 ABI compliant code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198149 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.Venkatraman Govindaraju2013-12-29
| | | | | | | Also, pass fp128 arguments to varargs through integer registers if necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198145 91177308-0d34-0410-b5e6-96231b3b80d8
* New machine model for cortex-a9. Schedule for resources and latency.Andrew Trick2013-12-28
| | | | | | | | | Schedule more conservatively to account for stalls on floating point resources and latency. Use the AGU resource to model latency stalls since it's shared between FP and LD/ST instructions. This might not be completely accurate but should work well in practice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198125 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/vselect.ll: Unbreak Windows x64 targets to add ↵NAKAMURA Takumi2013-12-28
| | | | | | -mtriple=x86_64-unknown-unknown. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198114 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Teach the backend how to fold target specific dag node for packedAndrea Di Biagio2013-12-28
| | | | | | | | | | | | | | | | | | | | | vector shift by immedate count (VSHLI/VSRLI/VSRAI) into a build_vector when the vector in input to the shift is a build_vector of all constants or UNDEFs. Target specific nodes for packed shifts by immediate count are in general introduced by function 'getTargetVShiftByConstNode' (in X86ISelLowering.cpp) when lowering shift operations, SSE/AVX immediate shift intrinsics and (only in very few cases) SIGN_EXTEND_INREG dag nodes. This patch adds extra rules for simplifying vector shifts inside function 'getTargetVShiftByConstNode'. Added file test/CodeGen/X86/vec_shift5.ll to verify that packed shifts by immediate are correctly folded into a build_vector when the input vector to the shift dag node is a vector of constants or undefs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198113 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR ofAndrea Di Biagio2013-12-27
| | | | | | | | | | | | | | | | | | | | | | ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198084 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju2013-12-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198030 91177308-0d34-0410-b5e6-96231b3b80d8
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