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* Revert 112442 and 112440 until the compile time problems introducedDan Gohman2010-09-01
| | | | | | | by 112440 are resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112692 91177308-0d34-0410-b5e6-96231b3b80d8
* We have a chance for an optimization. Consider this code:Bill Wendling2010-08-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | int x(int t) { if (t & 256) return -26; return 0; } We generate this: tst.w r0, #256 mvn r0, #25 it eq moveq r0, #0 while gcc generates this: ands r0, r0, #256 it ne mvnne r0, #25 bx lr Scandalous really! During ISel time, we can look for this particular pattern. One where we have a "MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND instruction to 0. Something like this (greatly simplified): %r0 = ISD::AND ... ARMISD::CMPZ %r0, 0 @ sets [CPSR] %r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR] All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR] when it's zero. The zero value will all ready be in the %r0 register and we only need to change it if the AND wasn't zero. Easy! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test for 112609Jim Grosbach2010-08-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112610 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix borken testAnton Korobeynikov2010-08-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112555 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NEON vmovn intrinsic, replacing it with vector truncate operations.Bob Wilson2010-08-30
| | | | | | | Auto-upgrade the old intrinsic and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
* two changes:Chris Lattner2010-08-30
| | | | | | | | | | | | | | 1) nuke ConstDataCoalSection, which is dead. 2) revise my previous patch for rdar://8018335, which was completely wrong. Specifically, it doesn't make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS, because it is for readonly data. templates (it turns out) go to const_coal_nt. The real fix for rdar://8018335 was to give ConstTextCoalSection a section kind of ReadOnly instead of Text. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112496 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct bogus module triple specifications.Duncan Sands2010-08-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112469 91177308-0d34-0410-b5e6-96231b3b80d8
* Make IVUsers iterative instead of recursive.Dan Gohman2010-08-29
| | | | | | | | This has the side effect of reversing the order of most of IVUser's results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112442 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test less dependent on register allocation choices.Dan Gohman2010-08-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112426 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-29
| | | | | | | The IDX was treated as byte index, not element index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvmBob Wilson2010-08-29
| | | | | | | | IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
* merge a bunch of shuffle tests into sse2.llChris Lattner2010-08-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112398 91177308-0d34-0410-b5e6-96231b3b80d8
* add some nounwind'sChris Lattner2010-08-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112396 91177308-0d34-0410-b5e6-96231b3b80d8
* fix the buildvector->insertp[sd] logic to not always create a redundantChris Lattner2010-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | insertp[sd] $0, which is a noop. Before: _f32: ## @f32 pshufd $1, %xmm1, %xmm2 pshufd $1, %xmm0, %xmm3 addss %xmm2, %xmm3 addss %xmm1, %xmm0 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm3, %xmm0 ret after: _f32: ## @f32 movdqa %xmm0, %xmm2 addss %xmm1, %xmm2 pshufd $1, %xmm1, %xmm1 pshufd $1, %xmm0, %xmm3 addss %xmm1, %xmm3 movdqa %xmm2, %xmm0 insertps $16, %xmm3, %xmm0 ret The extra movs are due to a random (poor) scheduling decision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112379 91177308-0d34-0410-b5e6-96231b3b80d8
* fix the BuildVector -> unpcklps logic to not do pointless shuffles Chris Lattner2010-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the top elements of a vector are undefined. This happens all the time for X86-64 ABI stuff because only the low 2 elements of a 4 element vector are defined. For example, on: _Complex float f32(_Complex float A, _Complex float B) { return A+B; } We used to produce (with SSE2, SSE4.1+ uses insertps): _f32: ## @f32 movdqa %xmm0, %xmm2 addss %xmm1, %xmm2 pshufd $16, %xmm2, %xmm2 pshufd $1, %xmm1, %xmm1 pshufd $1, %xmm0, %xmm0 addss %xmm1, %xmm0 pshufd $16, %xmm0, %xmm1 movdqa %xmm2, %xmm0 unpcklps %xmm1, %xmm0 ret We now produce: _f32: ## @f32 movdqa %xmm0, %xmm2 addss %xmm1, %xmm2 pshufd $1, %xmm1, %xmm1 pshufd $1, %xmm0, %xmm3 addss %xmm1, %xmm3 movaps %xmm2, %xmm0 unpcklps %xmm3, %xmm0 ret This implements rdar://8368414 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112378 91177308-0d34-0410-b5e6-96231b3b80d8
* Completely disable tail calls when fast-isel is enabled, as fast-iselDan Gohman2010-08-28
| | | | | | | doesn't currently support dealing with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112341 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-27
| | | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
* get this test passing on linux builders.Chris Lattner2010-08-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112280 91177308-0d34-0410-b5e6-96231b3b80d8
* Add alignment arguments to all the NEON load/store intrinsics.Bob Wilson2010-08-27
| | | | | | | | Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard ↵Daniel Dunbar2010-08-27
| | | | | | to find miscompiles with the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112250 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a hackaround for PR7993 which is causing failures on x86 builders that ↵Chris Lattner2010-08-26
| | | | | | lack sse2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112175 91177308-0d34-0410-b5e6-96231b3b80d8
* I think enough general codegen bugs are fixed to allow this to workChris Lattner2010-08-26
| | | | | | | on random hosts, lets see! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112172 91177308-0d34-0410-b5e6-96231b3b80d8
* implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.Chris Lattner2010-08-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112171 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure this forces the x86 targetsChris Lattner2010-08-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112169 91177308-0d34-0410-b5e6-96231b3b80d8
* fix sse1 only codegen in x86-64 mode, which is something weChris Lattner2010-08-26
| | | | | | | apparently try to support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112168 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable pre-RA virtual frame base register allocation. rdar://8277890Jim Grosbach2010-08-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112127 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert svn 107892 (with changes to work with trunk). It caused a crash ifBob Wilson2010-08-26
| | | | | | | | a VLD result was not used (Radar 8355607). It should also fix pr7988, but I haven't verified that yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112118 91177308-0d34-0410-b5e6-96231b3b80d8
* temporarily disable this, which started failing on the llvm-i686-linuxChris Lattner2010-08-25
| | | | | | | builder. I will investigate tonight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112113 91177308-0d34-0410-b5e6-96231b3b80d8
* Change handling of illegal vector types to widen when possible instead of Chris Lattner2010-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signedDaniel Dunbar2010-08-25
| | | | | | | | | comparison that would overflow. - The other under/overflow cases can't actually happen because the immediates which would trigger them are legal (so we don't enter this code), but adjusted the style to make it clear the transform is always valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
* Add another basic test cribbed from the x86 fast-isel tests.Eric Christopher2010-08-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112036 91177308-0d34-0410-b5e6-96231b3b80d8
* Run this on thumb and arm.Eric Christopher2010-08-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112035 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this testcase actually executed with fast-isel on arm.Eric Christopher2010-08-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112033 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert test to use filecheck and make it more specificBruno Cardoso Lopes2010-08-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112016 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix X86's isLegalAddressingMode to recognize that static addressesDan Gohman2010-08-24
| | | | | | | need not be RIP-relative in small mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111917 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-24
| | | | | | | llc used to assert on the added testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new llvm.x86.int intrinsic, allowing access to the Chris Lattner2010-08-23
| | | | | | | x86 int and int3 instructions. Patch by Peter Housel! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix x86 fast-isel's cmp+branch folding to avoid folding when theDan Gohman2010-08-21
| | | | | | | | | comparison is in a different basic block from the branch. In such cases, the comparison's operands may not have initialized virtual registers available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111709 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace some NEON vmovl intrinsic that I missed earlier.Bob Wilson2010-08-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111696 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend andBob Wilson2010-08-20
| | | | | | | zero-extend operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
* It's possible to sink a def if its local uses are PHI's.Evan Cheng2010-08-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111537 91177308-0d34-0410-b5e6-96231b3b80d8
* When sending stats output to stdout for grepping, don't emit normalDan Gohman2010-08-18
| | | | | | | output to standard output also. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111435 91177308-0d34-0410-b5e6-96231b3b80d8
* When sending stats output to stdout for grepping, don't emit normalDan Gohman2010-08-18
| | | | | | | output to standard output also. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111401 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-18
| | | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-18
| | | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
* Change SPU C calling convention to match that described in Kalle Raiskila2010-08-18
| | | | | | | | | "SPU Application Binary Interface Specification, v1.9" by IBM. Specifically: use r3-r74 to pass parameters and the return value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111358 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand ZERO_EXTEND operations for NEON vector types.Bob Wilson2010-08-18
| | | | | | | Testcase from Nick Lewycky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
* Tweak IVUsers' concept of "interesting" to exclude add recurrencesDan Gohman2010-08-17
| | | | | | | | | | where the step value is an induction variable from an outer loop, to avoid trouble trying to re-expand such expressions. This effectively hides such expressions from indvars and lsr, which prevents them from getting into trouble. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111317 91177308-0d34-0410-b5e6-96231b3b80d8
* Add nounwind.Evan Cheng2010-08-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111312 91177308-0d34-0410-b5e6-96231b3b80d8
* Make fast scheduler handle asm clobbers correctly.Dale Johannesen2010-08-17
| | | | | | | | PR 7882. Follows suggestion by Amaury Pouly, thanks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111306 91177308-0d34-0410-b5e6-96231b3b80d8
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