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* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-28
| | | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted outAkira Hatanaka2013-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-27
| | | | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: handle scalar TBAA format and struct-path aware TBAA format.Manman Ren2013-09-27
| | | | | | | | | | | | | | | | | Remove the command line argument "struct-path-tbaa" since we should not depend on command line argument to decide which format the IR file is using. Instead, we check the first operand of the tbaa tag node, if it is a MDNode, we treat it as struct-path aware TBAA format, otherwise, we treat it as scalar TBAA format. When clang starts to use struct-path aware TBAA format no matter whether struct-path-tbaa is no, and we can auto-upgrade existing bc files, the support for scalar TBAA format can be dropped. Existing testing cases are updated to use the struct-path aware TBAA format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191538 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rein back the use of block operationsRichard Sandiford2013-09-27
| | | | | | | | | | | | | | | The backend tries to use block operations like MVC, NC, OC and XC for simple scalar operations. For correctness reasons, it rejects any case in which the regions might partially overlap. However, for performance reasons, it should also reject cases where the regions might be equal, since the instruction might then not use the fast path. This fixes a performance regression seen in bzip2. We may want to limit the optimisation even more in future, or even remove it entirely, but I'll try with this for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve handling of PC-relative addressesRichard Sandiford2013-09-27
| | | | | | | | | | | | | | | The backend previously folded offsets into PC-relative addresses whereever possible. That's the right thing to do when the address can be used directly in a PC-relative memory reference (using things like LRL). But if we have a register-based memory reference and need to load the PC-relative address separately, it's better to use an anchor point that could be shared with other accesses to the same area of the variable. Fixes a FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-27
| | | | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-27
| | | | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-27
| | | | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove superfluous comment accidentally checked-in.Andrea Di Biagio2013-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191513 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for MSA registers to copyPhysRegDaniel Sanders2013-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-27
| | | | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply the change from r191393 with fix for pr17380.Andrea Di Biagio2013-09-27
| | | | | | | | | | | This change fixes the problem reported in pr17380 and re-add the dagcombine transformation ensuring that the value types are always legal if the transformation is triggered after Legalization took place. Added the test case from pr17380. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191509 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal ↵Daniel Sanders2013-09-27
| | | | | | error when using it in FR=0 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Expand all truncstores and loadexts for MSA as well as DSPDaniel Sanders2013-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191496 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added missing check in performSRACombineDaniel Sanders2013-09-27
| | | | | | | | | | Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D1755 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-26
| | | | | | | | t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo. This patch fixes it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191441 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.Bill Schmidt2013-09-26
| | | | | | | | | When generating code for shared libraries, even local calls may be intercepted, so we need a nop after the call for the linker to fix up the TOC. Test case adapted from the one provided in PR17354. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191440 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191393 since it caused pr17380.Andrea Di Biagio2013-09-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191438 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Implements exception handling in SPARC with DwarfCFI.Venkatraman Govindaraju2013-09-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191432 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-26
| | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-25
| | | | | | | | | | | | | | | | | | | | | Generally, it is desirable to distribute (a + b) * c to a*c + b*c for ARM with VMLx forwarding, where a, b and c are vectors. However, for (a + b)*(a + b), distribution will result in one extra instruction. With distribution: x = a + b (add) y = a * x (mul) z = y + b * y (mla) Without distribution: x = a + b (add) z = x * x (mul) This patch checks if a mul is a square of add/sub. If yes, skip distribution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit. Removed trailing whitespace.Josh Magee2013-09-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191402 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bad typo in the inline assembly code for mips16 pic fp stubsReed Kotler2013-09-25
| | | | | | | | | and make one cosmetic cleanup to make it look the same as gcc in this area; adjusting test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191400 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombiner how to canonicalize dags according to the ruleAndrea Di Biagio2013-09-25
| | | | | | | | | | | | | (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)). The rule only triggers when there are no other uses of the zext to avoid materializing more instructions. This helps the DAGCombiner understand that the shl/shr sequence can then be converted into an and instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191393 91177308-0d34-0410-b5e6-96231b3b80d8
* [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet2013-09-25
| | | | | | | | | | | | | | | | | | PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191349 91177308-0d34-0410-b5e6-96231b3b80d8
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-25
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing check to SETCC optimization.Eli Friedman2013-09-24
| | | | | | PR17338. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191337 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-24
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-24
| | | | | | IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Non-constant BUILD_VECTOR's should be expanded to ↵Daniel Sanders2013-09-24
| | | | | | | | | | INSERT_VECTOR_ELT instead of memory operations. The resulting code is the same length, but doesnt cause memory traffic or latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191297 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. ↵Daniel Sanders2013-09-24
| | | | | | | | | not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching andi, ori, nori, and xori from normal ↵Daniel Sanders2013-09-24
| | | | | | IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191293 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-24
| | | | | | (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-24
| | | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-24
| | | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching slli, srai, and srli from normal IR ↵Daniel Sanders2013-09-24
| | | | | | (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191285 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/AArch64/neon-scalar-reduce-pairwise.ll: Use -mtriple here, ↵NAKAMURA Takumi2013-09-24
| | | | | | or aach64-pecoff might be misassumed on win32 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191275 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-24
| | | | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Forgot to add in PR number to test case.Michael Gottesman2013-09-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191261 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Allow for copies from vreg -> vreg to be in a terminator ↵Michael Gottesman2013-09-24
| | | | | | | | | | | sequence. Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191260 91177308-0d34-0410-b5e6-96231b3b80d8
* Selecting the address from a very long chain of GEPs can blow the stack.Bill Wendling2013-09-24
| | | | | | | | | | | The recursive nature of the address selection code can cause the stack to explode if there is a long chain of GEPs. Convert the recursive bit into a iterative method to avoid this. <rdar://problem/12445434> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191252 91177308-0d34-0410-b5e6-96231b3b80d8
* Make nomips16 mask not repeat if it ends with a '.'.Reed Kotler2013-09-23
| | | | | | | | This mask is purely for debugging and testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191231 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sha intrinsic testsBen Langmuir2013-09-23
| | | | | | | These should have been included with r190864, but I forgot to use svn add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191208 91177308-0d34-0410-b5e6-96231b3b80d8
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