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* Platform proof a test case.Andrew Trick2013-11-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194788 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-15
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all the conditional Mips 16 branches get initially set for theReed Kotler2013-11-15
| | | | | | | | | | | | short form. Constant islands will expand them if they are out of range. Since there is not direct object emitter at this time, it does not have any material affect because the assembler sorts this out. But we need to know for the actual constant island work. We track the difference by putting # 16 inst in the comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
* Add addrspacecast instruction.Matt Arsenault2013-11-15
| | | | | | Patch by Michele Scandale! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify testcase.Eric Christopher2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194748 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: produce friendly error for invalid inline asmTim Northover2013-11-14
| | | | | | | | | We used to perform an invalid operation on an MVT and crash, which wasn't much fun. Patch by Oliver Stannard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194714 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple and switch test to FileCheck.Rafael Espindola2013-11-14
| | | | | | | On windows we don't print .weak for function definitions, so count was only finding 1 'weak'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194713 91177308-0d34-0410-b5e6-96231b3b80d8
* Error if we see an alias to a declaration.Rafael Espindola2013-11-14
| | | | | | | | | | | | | | | In ELF and COFF an alias is just another offset in a section. There is no way to represent an alias to something in another file. In MachO, the spec has the N_INDR type which should allow for exactly that, but is not currently implemented. Given that it is specified but not implemented, we error in codegen to avoid miscompiling but don't reject aliases to declarations in the verifier to leave the option open of implementing it. In the past we have used alias to declarations as a way of implementing weakref, which is why it exists in some old tests which this patch updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194705 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Handled extractelement from mask vector;Elena Demikhovsky2013-11-14
| | | | | | | Added VMOSHDUP/VMOVSLDUP shuffle instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add testcase for problem I ran intoMatt Arsenault2013-11-14
| | | | | | with the older version of the moveToVALU changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194682 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor extension to llvm.experimental.patchpoint: don't require a call.Andrew Trick2013-11-14
| | | | | | | | If a null call target is provided, don't emit a dummy call. This allows the runtime to reserve as little nop space as it needs without the requirement of emitting a call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194676 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case for AArch64 NEON instruction set misc.Kevin Qin2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't mangle \n and "Rafael Espindola2013-11-14
| | | | | | | | | | There is nothing special about quotes and newlines from the object file point of view, only the assembler has to worry about expanding the \n and \". This patch then removes the special handling from the Mangler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194667 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction class SIMD misc.Kevin Qin2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
* Take care of long short branch immediate instructions for mips16 inReed Kotler2013-11-13
| | | | | | | | constant islands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194630 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-13
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-13
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for legacy AArch32 NEON scalar shift by immediateChad Rosier2013-11-13
| | | | | | | | instructions. This patch does not include the shift right and accumulate instructions. A number of non-overloaded intrinsics have been remove in favor of their overloaded counterparts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194598 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-13
| | | | | | | | | | | | | | | | By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove AllowQuotesInName and friends from MCAsmInfo.Rafael Espindola2013-11-13
| | | | | | | | | | | Accepting quotes is a property of an assembler, not of an object file. For example, ELF can support any names for sections and symbols, but the gnu assembler only accepts quotes in some contexts and llvm-mc in a few more. LLVM should not produce different symbols based on a guess about which assembler will be reading the code it is printing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194575 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: implement exception handlingRobert Lytton2013-11-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194564 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the code which returns the length for inline assembler to knowReed Kotler2013-11-13
| | | | | | | | | | | specifically about the .space directive. This allows us to force large blocks of code to appear in test cases for things like constant islands without having to make giant test cases to force things like long branches to take effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194555 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case to verify that misusing anyregcc crashes as expected.Andrew Trick2013-11-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194553 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194547 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-11-13
| | | | | | | | | | | | | | | | | | | | | | This patch reapplies r193676 with an additional fix for the Hexagon backend. The SystemZ backend has already been fixed by r194148. The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask type for the given target. Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. Reviewed by Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194542 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup the stackmap operand folding code and fix a corner case.Andrew Trick2013-11-12
| | | | | | | I still don't know how to refer to the fixed operands symbolically. I plan to look into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194529 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix a bug in function CC_MipsO32_FP64. The second double precisionAkira Hatanaka2013-11-12
| | | | | | | | argument was not being passed in $f14. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Run test case with command line option -mattr=+fp64.Akira Hatanaka2013-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194519 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix and re-enable a test case that has been disabled for a long time.Akira Hatanaka2013-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify operand folding when rematerializing a load.Andrew Trick2013-11-12
| | | | | | | | | | | | We already know how to fold a reload from a frameindex without analyzing the load instruction. Generalize this to handle any frameindex load. This streamlines the logic for rematerializing loads from stack arguments. As a side effect, it allows stackmaps to record a stack argument location without spilling it. Verified no effect on codegen for llvm test-suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194497 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-12
| | | | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-12
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add support for FP_HP_extension build attributeBradley Smith2013-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194470 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from ↵Daniel Sanders2013-11-12
| | | | | | normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Change constant used in ori tests to avoid conflict with bseti ↵Daniel Sanders2013-11-12
| | | | | | | | | | | | | | (also xori to avoid bnegi) Upcoming commit(s) are going to add support for bseti and bnegi. This would cause some existing tests to (correctly) change behaviour and emit a different instruction. This patch prevents this by changing the constant used in ori and xori tests so that they will not be matchable by the bseti and bnegi patterns when these instructions are matchable from normal IR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194467 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix bug in aligning 'byval i8*' on the stackRobert Lytton2013-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194466 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target test for hidden declarationRobert Lytton2013-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194465 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore support for ATOMIC_FENCE.Robert Lytton2013-11-12
| | | | | | | | | | ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There is no need to emit an instructions since the XCore provides sequential consistency. Original patch by Richard Osborne git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194464 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: return error for unsupported alignmentRobert Lytton2013-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194463 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-12
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-12
| | | | | | | | | | | | | This has no material effect at this time since we don't have a direct object emitter for mips16 and the assembler can't tell them apart. I place a comment "16 bit inst" for those so that I can tell them apart in the output. The constant island pass has only been minimally changed to allow this. More complete branch work is forthcoming but this is the first step. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add test that fails due to requiring i64 mul for pointersMatt Arsenault2013-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194433 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the recently added anyregcc convention to handle spilled operands.Andrew Trick2013-11-11
| | | | | | | | | | | | Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!" The primary purpose of anyregcc is to prevent a patchpoint's call arguments and return value from being spilled. They must be available in a register, although the calling convention does not pin the register. It's up to the front end to avoid using this convention for calls with more arguments than allocatable registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194428 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-11
| | | | | | | | the floating point register mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194423 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment ↵Justin Holewinski2013-11-11
| | | | | | of function parameters git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194410 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix logic error in loading vector parameters of more than 4 componentsJustin Holewinski2013-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194409 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-11
| | | | | | source operands, a vector, an element to insert, and a shift amount. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194406 91177308-0d34-0410-b5e6-96231b3b80d8
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