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* Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to ↵Craig Topper2011-12-30
| | | | | | force alignment on these instructions. Add a couple testcases for memory forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 ↵Craig Topper2011-12-30
| | | | | | size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup stack/frame register define/kill states. This fixes two bugs:Hal Finkel2011-12-30
| | | | | | | | 1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test). 2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix type-checking for load transformation which is not legal on ↵Eli Friedman2011-12-28
| | | | | | floating-point types. PR11674. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8
* PR11662.Nadav Rotem2011-12-28
| | | | | | | | | Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147309 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.Elena Demikhovsky2011-12-28
| | | | | | | | | Matching MOVLP mask for AVX (265-bit vectors) was wrong. The failure was detected by conformance tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman2011-12-26
| | | | | | location. PR10747, part 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147283 91177308-0d34-0410-b5e6-96231b3b80d8
* Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when theChandler Carruth2011-12-24
| | | | | | | | | | | | | | | | | | LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
* Add systematic testing for cttz as well, and fix the bug I spotted byChandler Carruth2011-12-24
| | | | | | inspection earlier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147250 91177308-0d34-0410-b5e6-96231b3b80d8
* Add i8 and i64 testing for ctlz on x86. Also simplify the i16 test.Chandler Carruth2011-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147249 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up this rather crufty test. Put the declarations at the top to makeChandler Carruth2011-12-24
| | | | | | | | | | | | | my C-brain happy. Remove the unnecessary bits of pedantic IR fluff like nounwind. Remove stray uses comments. Name things semantically rather than tN so that adding a new test in the middle doesn't cause pain, and so that new tests can be grouped semantically. This exposes how little systematic testing is going on here. I noticed this by finding several bugs via inspection and wondering why this test wasn't catching any of them. =[ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147248 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand more when we have a nice 'tzcnt' instruction, to avoid generatingChandler Carruth2011-12-24
| | | | | | | | | | | 'bsf' instructions here. This one is actually debatable to my eyes. It's not clear that any chip implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding. Still, this restores the old behavior with 'tzcnt' enabled for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up some of these tests.Chandler Carruth2011-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147245 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to theChandler Carruth2011-12-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | X86ISelLowering C++ code. Because this is lowered via an xor wrapped around a bsr, we want the dagcombine which runs after isel lowering to have a chance to clean things up. In particular, it is very common to see code which looks like: (sizeof(x)*8 - 1) ^ __builtin_clz(x) Which is trying to compute the most significant bit of 'x'. That's actually the value computed directly by the 'bsr' instruction, but if we match it too late, we'll get completely redundant xor instructions. The more naive code for the above (subtracting rather than using an xor) still isn't handled correctly due to the dagcombine getting confused. Also, while here fix an issue spotted by inspection: we should have been expanding the zero-undef variants to the normal variants when there is an 'lzcnt' instruction. Do so, and test for this. We don't want to generate unnecessary 'bsr' instructions. These two changes fix some regressions in encoding and decoding benchmarks. However, there is still a *lot* to be improve on in this type of code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup this test a bit, sorting things and grouping them more clearly.Chandler Carruth2011-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147243 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r147232.Akira Hatanaka2011-12-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147233 91177308-0d34-0410-b5e6-96231b3b80d8
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-23
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of copy-n-paste bugs. Noticed by George Russell!Chad Rosier2011-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of copy-n-paste bugs. Noticed by George Russell.Evan Cheng2011-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in zero-store peephole pattern reported in pr11615.Akira Hatanaka2011-12-21
| | | | | | | | The patch and test case were originally written by Mans Rullgard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand 64-bit CTLZ nodes if target architecture does not support it. Add testAkira Hatanaka2011-12-21
| | | | | | | case for DCLO and DCLZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r147017.Akira Hatanaka2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147018 91177308-0d34-0410-b5e6-96231b3b80d8
* Add function MipsDAGToDAGISel::SelectMULT and factor out code that generatesAkira Hatanaka2011-12-20
| | | | | | | | | nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
* 64-bit data directive.Akira Hatanaka2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
* 32-to-64-bit sext_inreg pattern.Akira Hatanaka2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
* Add code in MipsDAGToDAGISel for selecting constant +0.0.Akira Hatanaka2011-12-20
| | | | | | | MIPS64 can generate constant +0.0 with a single DMTC1 instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
* Heed spill slot alignment on ARM.Jakob Stoklund Olesen2011-12-20
| | | | | | | | | | | Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the second fix related to VZEXT_MOVL node.Elena Demikhovsky2011-12-20
| | | | | | | | | | | | | | | | | | | | | | The failure that I see in the current version is: LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14] 0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13] 0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12] 0x18b9870: v4i64 = undef [ID=4] 0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10] 0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9770: i32 = TargetConstant<0> [ID=6] 0x18b9970: i32 = Constant<0> [ID=3] 0x18b9170: v2i64 = undef [ORD=1] [ID=1] 0x18b9570: i32 = Constant<2> [ID=5] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin teaching the X86 target how to efficiently codegen patterns thatChandler Carruth2011-12-20
| | | | | | | | | | | | | | | use the zero-undefined variants of CTTZ and CTLZ. These are just simple patterns for now, there is more to be done to make real world code using these constructs be optimized and codegen'ed properly on X86. The existing tests are spiffed up to check that we no longer generate unnecessary cmov instructions, and that we generate the very important 'xor' to transform bsr which counts the index of the most significant one bit to the number of leading (most significant) zero bits. Also they now check that when the variant with defined zero result is used, the cmov is still produced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson2011-12-20
| | | | | | | | | | | | We used to rely on the *eh_sjlj_setjmp instructions to mark that a function with setjmp/longjmp exception handling clobbers all the registers. But with the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are expanded away earlier, before PEI can see them to determine what registers to save and restore. Mark the dispatchsetup instruction in the same way, since that instruction cannot be expanded early. This also more accurately reflects when the registers are clobbered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949 91177308-0d34-0410-b5e6-96231b3b80d8
* Move tests to FileCheck.Evan Cheng2011-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146923 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for r146900.Akira Hatanaka2011-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146901 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for matching immediates whose lower 16-bit is cleared. TheseAkira Hatanaka2011-12-19
| | | | | | | | patterns emit a single LUi instruction instead of a pair of LUi and ORi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove definitions of double word shift plus 32 instructions. Assembler orAkira Hatanaka2011-12-19
| | | | | | | | | direct-object emitter should emit the appropriate shift instruction depending on the shift amount. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-19
| | | | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.Evan Cheng2011-12-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure that the lower bits on the VSELECT condition are properly set.Lang Hames2011-12-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix off-by-one error in bucket sort.Jakob Stoklund Olesen2011-12-16
| | | | | | | | | The bad sorting caused a misaligned basic block when building 176.vpr in ARM mode. <rdar://problem/10594653> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Fix a nasty order-of-initialization bug.Benjamin Kramer2011-12-16
| | | | | | Reenable the tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is ↵Craig Topper2011-12-16
| | | | | | supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146726 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing zmovl AVX patterns which were causing crashes.Chad Rosier2011-12-15
| | | | | | Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146689 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.Chad Rosier2011-12-15
| | | | | | Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146684 91177308-0d34-0410-b5e6-96231b3b80d8
* Set specific target cpu for testcase.Lang Hames2011-12-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146678 91177308-0d34-0410-b5e6-96231b3b80d8
* Added test case for r146671.Lang Hames2011-12-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146675 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case to make sure that the nop really does follow the bl on ppc64 elfHal Finkel2011-12-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146666 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman2011-12-15
| | | | | | but the existing code can't do it correctly. PR11570. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for lowering fneg when AVX is enabled.Chad Rosier2011-12-15
| | | | | | | rdar://10566486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not sink instruction, if it is not profitable.Devang Patel2011-12-14
| | | | | | | | | On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146604 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-14
| | | | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
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