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* DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer ↵David Blaikie2014-02-04
| | | | | | | | | | | emits zero-length arrays as {i32 0} A bunch of test cases needed to be cleaned up for this, many my fault - when implementid imported modules I updated test cases by simply duplicating the prior metadata field - which wasn't always the empty metadata entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200731 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64 & ARM: refactor crypto intrinsics to take scalarsTim Northover2014-02-03
| | | | | | | | | | | | Some of the SHA instructions take a scalar i32 as one argument (largely because they work on 160-bit hash fragments). This wasn't reflected in the IR previously, with ARM and AArch64 choosing different types (<4 x i32> and <1 x i32> respectively) which was ugly. This makes all the affected intrinsics take a uniform "i32", allowing them to become non-polymorphic at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200706 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand vector bswap in LegalizeVectorOpsHal Finkel2014-02-03
| | | | | | | ISD::BSWAP was missing from the list of node types that should be expanded element-wise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200705 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some xfailed R600 tests for 64-bit private accesses.Matt Arsenault2014-02-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200620 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix insertelement with dynamic indices.Matt Arsenault2014-02-02
| | | | | | | | This didn't work for any integer vectors, and didn't work with some sizes of float vectors. This should now work with all sizes of float and i32 vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200619 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Set %o7 as the return address register instead of %i7 in ↵Venkatraman Govindaraju2014-02-01
| | | | | | MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200617 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Implement the sspstrong rules for stack layout.Josh Magee2014-02-01
| | | | | | | | | | | | | | | | | | | This changes the PrologueEpilogInserter and LocalStackSlotAllocation passes to follow the extended stack layout rules for sspstrong and sspreq. The sspstrong layout rules are: 1. Large arrays and structures containing large arrays (>= ssp-buffer-size) are closest to the stack protector. 2. Small arrays and structures containing small arrays (< ssp-buffer-size) are 2nd closest to the protector. 3. Variables that have had their address taken are 3rd closest to the protector. Differential Revision: http://llvm-reviews.chandlerc.com/D2546 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200601 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement inalloca codegen for x86 with the new inalloca designReid Kleckner2014-01-31
| | | | | | | | | | | | | | | | Calls with inalloca are lowered by skipping all stores for arguments passed in memory and the initial stack adjustment to allocate argument memory. Now the frontend is responsible for the memory layout, and the backend doesn't have to do any work. As a result these changes are pretty minimal. Reviewers: echristo Differential Revision: http://llvm-reviews.chandlerc.com/D2637 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200596 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't put non-static allocas in the static alloca mapReid Kleckner2014-01-31
| | | | | | | | Allocas marked inalloca are never static, but we were trying to put them into the static alloca map if they were in the entry block. Also add an assertion in x86 fastisel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200593 91177308-0d34-0410-b5e6-96231b3b80d8
* Set -mcpu to make this test pass on atom botsReid Kleckner2014-01-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200588 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace X86 FMA intrinsic pseduo-instructions with def pats.Lang Hames2014-01-31
| | | | | | | | | | | | | It looks like these pseudos were only used for pattern matching. Def pats are the appropriate way to do that. As a bonus, these intrinsics will now have memory operands folded properly, and better FMA3 variants selected where appropriate (see r199933). <rdar://problem/15611947> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200577 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'Reid Kleckner2014-01-31
| | | | | | | | | | | | | | | | | | | | MSVC always places the 'this' parameter for a method first. The implicit 'sret' pointer for methods always comes second. We already implement this for __thiscall by putting sret parameters on the stack, but __cdecl methods require putting both parameters on the stack in opposite order. Using a special calling convention allows frontends to keep the sret parameter first, which avoids breaking lots of assumptions in LLVM and Clang. Fixes PR15768 with the corresponding change in Clang. Reviewers: ributzka, majnemer Differential Revision: http://llvm-reviews.chandlerc.com/D2663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200561 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add insert.d instruction.Matheus Almeida2014-01-31
| | | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200543 91177308-0d34-0410-b5e6-96231b3b80d8
* Update FileCheck prefixes in preparation for the addition of Mips64 MSA tests.Matheus Almeida2014-01-31
| | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200541 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch teaches the DAGCombiner how to fold insert_subvector nodesManman Ren2014-01-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the input is a concat_vectors and the insert replaces one of the concat halves: Lower half: fold (insert_subvector (concat_vectors X, Y), Z) -> (concat_vectors Z, Y) Upper half: fold (insert_subvector (concat_vectors X, Y), Z) -> (concat_vectors X, Z) This can be seen with the following IR: define <8 x float> @lower_half(<4 x float> %v1, <4 x float> %v2, <4 x float> %v3) { %1 = shufflevector <4 x float> %v1, <4 x float> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %2 = tail call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %1, <4 x float> %v3, i8 0) The vinsertf128 intrinsic is converted into an insert_subvector node in SelectionDAGBuilder.cpp. Using AVX, without the patch this generates two vinsertf128 instructions: vinsertf128 $1, %xmm1, %ymm0, %ymm0 vinsertf128 $0, %xmm2, %ymm0, %ymm0 With the patch this is optimized into: vinsertf128 $1, %xmm1, %ymm2, %ymm0 Patch by Robert Lougher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200506 91177308-0d34-0410-b5e6-96231b3b80d8
* PGO branch weight: update edge weights in SelectionDAGBuilder.Manman Ren2014-01-31
| | | | | | | | | | | | | | | | | When converting from "or + br" to two branches, or converting from "and + br" to two branches, we correctly update the edge weights of the two branches. The previous attempt at r200431 was reverted at r200434 because of two testing case failures. I modified my patch a little, but forgot to re-run "make check-all". Testing case CodeGen/ARM/lsr-unfolded-offset.ll is updated because of the patch's impact on branch probability which causes changes in spill placement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200502 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Custom lower concat_vector patterns with v4i16, v4i32, v8i8, ↵Chad Rosier2014-01-30
| | | | | | v8i16, v16i8 types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200491 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmaps] Record the stack size of each function that contains a ↵Juergen Ributzka2014-01-30
| | | | | | | | | | stackmap/patchpoint intrinsic. Re-applying the patch, but this time without using AsmPrinter methods. Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200481 91177308-0d34-0410-b5e6-96231b3b80d8
* Reenable ARM EHABI on Android.Evgeniy Stepanov2014-01-30
| | | | | | | Broken in r200388. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200466 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement SPARCv9 atomic_swap_64 with a pseudo.Jakob Stoklund Olesen2014-01-30
| | | | | | | | The SWAP instruction only exists in a 32-bit variant, but the 64-bit atomic swap can be implemented in terms of CASX, like the other atomic rmw primitives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200453 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "[Stackmaps] Record the stack size of each function that contains a ↵Juergen Ributzka2014-01-30
| | | | | | | | stackmap/patchpoint intrinsic." This reverts commit r200444 to unbreak buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200445 91177308-0d34-0410-b5e6-96231b3b80d8
* [Stackmaps] Record the stack size of each function that contains a ↵Juergen Ributzka2014-01-30
| | | | | | | | stackmap/patchpoint intrinsic. Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200444 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r200431 due to bot failures.Manman Ren2014-01-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200434 91177308-0d34-0410-b5e6-96231b3b80d8
* PGO branch weight: update edge weights in SelectionDAGBuilder.Manman Ren2014-01-30
| | | | | | | | | When converting from "or + br" to two branches, or converting from "and + br" to two branches, we correctly update the edge weights of the two branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200431 91177308-0d34-0410-b5e6-96231b3b80d8
* PGO branch weight: update edge weights in IfConverter.Manman Ren2014-01-29
| | | | | | | | | | | | | | This commit only handles IfConvertTriangle. To update edge weights of a successor, one interface is added to MachineBasicBlock: /// Set successor weight of a given iterator. setSuccWeight(succ_iterator I, uint32_t weight) An existing testing case test/CodeGen/Thumb2/v8_IT_5.ll is updated, since we now correctly update the edge weights, the cold block is placed at the end of the function and we jump to the cold block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200428 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add fill.d instruction.Matheus Almeida2014-01-29
| | | | | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200400 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2r_vector_scalar.ll test.Matheus Almeida2014-01-29
| | | | | | | | | | This update is a preparation for the addition of Mips64 MSA tests. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200399 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Add copy_{u,s}.d.Matheus Almeida2014-01-29
| | | | | | | | | These instructions are only available on Mips64 cores that implement the MSA ASE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200398 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA elm_copy.ll test.Matheus Almeida2014-01-29
| | | | | | | | | | This update is a preparation for the addition of Mips64 MSA tests. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200395 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable EHABI by defaultRenato Golin2014-01-29
| | | | | | | | | | | | | | | | | | | | | | After all hard work to implement the EHABI and with the test-suite passing, it's time to turn it on by default and allow users to disable it as a work-around while we fix the eventual bugs that show up. This commit also remove the -arm-enable-ehabi-descriptors, since we want the tables to be printed every time the EHABI is turned on for non-Darwin ARM targets. Although MCJIT EHABI is not working yet (needs linking with the right libraries), this commit also fixes some relocations on MCJIT regarding the EH tables/lib calls, and update some tests to avoid using EH tables when none are needed. The EH tests in the test-suite that were previously disabled on ARM now pass with these changes, so a follow-up commit on the test-suite will re-enable them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200388 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Use %r_disp32 for pc_rel entries in FDE as well.Venkatraman Govindaraju2014-01-29
| | | | | | | | This makes MCAsmInfo::getExprForFDESymbol() a virtual function and overrides it in SparcMCAsmInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200376 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.Venkatraman Govindaraju2014-01-29
| | | | | | | | | Otherwise, assembler (gas) fails to assemble them with error message "operation combines symbols in different segments". This is because MC computes pc_rel entries with subtract expression between labels from different sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200373 91177308-0d34-0410-b5e6-96231b3b80d8
* [SparcV9] Use correct register class (I64RegClass) to hold the address of ↵Venkatraman Govindaraju2014-01-29
| | | | | | _GLOBAL_OFFSET_TABLE_ in sparcv9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200368 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a raw_stream to implement the mangler.Rafael Espindola2014-01-29
| | | | | | | | | This is a bit more convenient for some callers, but more importantly, it is easier to implement correctly. Doing this removes the patching of already printed data that was used for fastcall, fixing a crash with private fastcall symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200367 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Lower SELECT_CC with vector operand.Kevin Qin2014-01-29
| | | | | | | | When the scalar compare is between floating point and operands are vector, we custom lower SELECT_CC to use NEON SIMD compare for generating less instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200365 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Remove superfluous inline asm mode switch testDavid Woodhouse2014-01-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200361 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests for mode switchingDavid Woodhouse2014-01-28
| | | | | | | 1. test that inlineasm works 2. test that relaxable instructions are re-encoded in the correct mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200351 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix emitting aggregate parametersGautam Chakrabarti2014-01-28
| | | | | | | | | | The code was missing the case for aggregate parameters and hence was emitting them as .b0 type. Also fixed a couple of comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200325 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add extra rules for combining vselect dag nodes into movsd.Andrea Di Biagio2014-01-28
| | | | | | | | | | | | | | | | | | | | | | This improves the fix committed at revision 199683 adding the following new target specific combine rules: 1) fold (v4i32: vselect <0,0,-1,-1>, A, B) -> (v4i32 (bitcast (movsd (v2i64 (bitcast A)), (v2i64 (bitcast B))) )) 2) fold (v4f32: vselect <0,0,-1,-1>, A, B) -> (v4f32 (bitcast (movsd (v2f64 (bitcast A)), (v2f64 (bitcast B))) )) 3) fold (v4i32: vselect <-1,-1,0,0>, A, B) -> (v4i32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) )) 4) fold (v4f32: vselect <-1,-1,0,0>, A, B) -> (v4f32 (bitcast (movsd (v2i64 (bitcast B)), (v2i64 (bitcast A))) )) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200324 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Avoid introducing an illegal build_vector when folding a ↵Andrea Di Biagio2014-01-28
| | | | | | | | | | | | | | | | | | sign_extend. Make sure that we don't introduce illegal build_vector dag nodes when trying to fold a sign_extend of a build_vector. This fixes a regression introduced by r200234. Added test CodeGen/X86/fold-vector-sext-crash.ll to verify that llc no longer crashes with an assertion failure due to an illegal build_vector of type MVT::v4i64. Thanks to Ilia Filippov for spotting this regression and for providing a reproducible test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200313 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle spilling the PPC GPRC_NOR0 register classHal Finkel2014-01-28
| | | | | | | GPRC_NOR0 is not a subclass of GPRC (because it also contains the ZERO pseudo register). As a result, we also need to check for it in the spilling code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200288 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for truncating i32 to i1Michel Danzer2014-01-28
| | | | | | | | Fixes half a dozen piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200283 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the DWARF EH encodings for Sparc PIC code.Jakob Stoklund Olesen2014-01-28
| | | | | | | Also emit the stubs that were generated for references to typeinfo symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200282 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix unsupported addressing mode assertion for pldDavid Peixotto2014-01-27
| | | | | | | | | | | | | | | | | | | | Summary: This commit gives an address mode to the PLD instruction. We were getting an assertion failure in the frame lowering code because we had code that was doing a pld of a stack allocated address. The frame lowering was checking the address mode and then asserting because pld had none defined. This commit fixes pld for arm mode. There was a previous fix for thumb mode in a separate commit. The commit for thumb mode added a test in a separate file because it would otherwise fail for arm. This commit moves the thumb test back into the prefetch.ll file and adds the corresponding arm test. Differential Revision: http://llvm-reviews.chandlerc.com/D2622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200248 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Teach how to fold sext/aext/zext of constant build vectors.Andrea Di Biagio2014-01-27
| | | | | | | | | | | | | | | This patch teaches the DAGCombiner how to fold a sext/aext/zext dag node when the operand in input is a build vector of constants (or UNDEFs). The inability to fold a sext/zext of a constant build_vector was the root cause of some pcg bugs affecting vselect expansion on x86-64 with AVX support. Before this change, the DAGCombiner only knew how to fold a sext/zext/aext of a ConstantSDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200234 91177308-0d34-0410-b5e6-96231b3b80d8
* Additional fix for 200201: due to dependence on bitwidth test was moved to ↵Stepan Dyatkovskiy2014-01-27
| | | | | | X86 directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200202 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR18102.Stepan Dyatkovskiy2014-01-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue outcomes from DAGCombiner::MergeConsequtiveStores, more precisely from mem-ops sequence sorting. Consider, how MergeConsequtiveStores works for next example: store i8 1, a[0] store i8 2, a[1] store i8 3, a[1] ; a[1] again. return ; DAG starts here 1. Method will collect all the 3 stores. 2. It sorts them by distance from the base pointer (farthest with highest index). 3. It takes first consecutive non-overlapping stores and (if possible) replaces them with a single store instruction. The point is, we can't determine here which 'store' instruction would be the second after sorting ('store 2' or 'store 3'). It happens that 'store 3' would be the second, and 'store 2' would be the third. So after merging we have the next result: store i16 (1 | 3 << 8), base ; is a[0] but bit-casted to i16 store i8 2, a[1] So actually we swapped 'store 3' and 'store 2' and got wrong contents in a[1]. Fix: In sort routine just also take into account mem-op sequence number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200201 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructionsMichel Danzer2014-01-27
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200196 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsic for S_SENDMSG instructionMichel Danzer2014-01-27
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200195 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64 NEON] Try to generate CONCAT_VECTOR when lowering BUILD_VECTOR or ↵Kevin Qin2014-01-27
| | | | | | | | SHUFFLE_VECTOR. Replace r199791. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200180 91177308-0d34-0410-b5e6-96231b3b80d8
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