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* [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 ↵Artyom Skrobov2013-11-08
| | | | | | as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
* Return early from getUnconditionalBranchTargetOpValue if the branch target isLang Hames2013-10-28
| | | | | | | | | | | | | | | | | | | an MCExpr, in order to avoid writing an encoded zero value in the immediate field. When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we don't know what the final immediate field value should be. We shouldn't explicitly set the immediate field to an encoded zero value as zero is encoded with a non-zero bit pattern. This leads to bits being set that pollute the final immediate value. The nature of the encoding is such that the polluted bits only affect very large immediate values, explaining why this hasn't caused problems earlier. Fixes <rdar://problem/15155975>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193535 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-18
| | | | | | | | Patch by Artyom Skrobov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-21
| | | | | | | | According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 add immediate alias for SPMihai Popa2013-08-19
| | | | | | | | | | The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction. All the patch does is adjust a register constraint on an instruction alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188676 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for Thumb2 literal loads with negative zero offsetMihai Popa2013-08-16
| | | | | | | | | | Thumb2 literal loads use an offset encoding which allows for negative zero. This fixes parsing and encoding so that #-0 is correctly processed. The parser represents #-0 as INT32_MIN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188549 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Thumb2 aliasing complementary instructions taking modified immediatesMihai Popa2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | There are many Thumb instructions which take 12-bit immediates encoded in a special 8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal to transform an assembly instruction to be able to encode the immediate. For example: AND and BIC are complementary instructions; one can switch the AND to a BIC as long as the immediate is complemented. The intent is to switch one instruction into its complementary one when the immediate cannot be encoded in the form requested in the original assembly and when the complementary immediate is encodable. The patch addresses two issues: 1. definition of t2SOImmNot immediate - it has to check that the orignal value is not encoded naturally 2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand rather than the ARM one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188548 91177308-0d34-0410-b5e6-96231b3b80d8
* This fixes three issues related to Thumb literal loads:Mihai Popa2013-08-15
| | | | | | | | | | 1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020] 2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed 3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen and the ASM parser, so this alias rule really does nothing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-09
| | | | | | | | | | | | | | | In Thumb1, only one variant is supported: CPS{effect} {flags} Thumb2 supports three: CPS{effect}.W {flags} CPS{effect} {flags} {mode} CPS {mode} Canonically, .W should be used only when ambiguity is present between encodings of different width. The wide suffix is still accepted for the latter two forms via aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188071 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling of Thumb2 branch instructions.Mihai Popa2013-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The long encoding for Thumb2 unconditional branches is broken. Additionally, there is no range checking for target operands; as such for instructions originating in assembly code, only short Thumb encodings are generated, regardless of the bitsize needed for the offset. Adding range checking is non trivial due to the representation of Thumb branch instructions. There is no true difference between conditional and unconditional branches in terms of operands and syntax - even unconditional branches have a predicate which is expected to match that of the IT block they are in. Yet, the encodings and the permitted size of the offset differ. Due to this, for any mnemonic there are really 4 encodings to choose for. The problem cannot be handled in the parser alone or by manipulating td files. Because the parser builds first a set of match candidates and then checks them one by one, whatever tablegen-only solution might be found will ultimately be dependent of the parser's evaluation order. What's worse is that due to the fact that all branches have the same syntax and the same kinds of operands, that order is governed by the lexicographical ordering of the names of operand classes... To circumvent all this, any necessary disambiguation is added to the instruction validation pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
* Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc ↵Mihai Popa2013-08-06
| | | | | | instead of apsr_nzcv) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-31
| | | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-22
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.Tilmann Scheller2013-07-19
| | | | | | | | | | See A8.8.127 in ARM DDI 0406C.b. Related to <rdar://problem/14403733>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186682 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add support for the Thumb2 PLI alternate literal form.Tilmann Scheller2013-07-16
| | | | | | | | | | | | This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>] See A8.8.129 in the ARM ARM (DDI 0406C.b). Fixes <rdar://problem/14403733>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186459 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying ↵Tilmann Scheller2013-07-03
| | | | | | | | | | | | | | | | certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-03
| | | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMAsmParser] Sort the ARM register lists based on the encoding value, not theChad Rosier2013-07-01
| | | | | | | tablegen enum values. This should be the last fix due to fallout from r185094. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix pseudo-instructions for SRS (Store Return State).Tilmann Scheller2013-06-28
| | | | | | | | | | | | | | | The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is: srsfa -> srsib srsea -> srsia srsfd -> srsdb srsed -> srsda This fixes <rdar://problem/14214734>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185155 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix literal load with positive offset encodingAmaury de la Vieuville2013-06-18
| | | | | | | | | | | | When using a positive offset, literal loads where encoded as if it was negative, because: - The sign bit was not assigned to an operand - The addrmode_imm12 operand was not encoding the sign bit correctly This patch also makes the assembler look at the .w/.n specifier for loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix t2am_imm8_offset operand printing for imm=#-0Amaury de la Vieuville2013-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183913 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-10
| | | | | | ISB should only accepts full system sync, other options are reserved git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-26
| | | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-23
| | | | | | | | Handle an implied 'sp' operand. rdar://11466783 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby2012-12-14
| | | | | | | | | immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-02
| | | | | | index issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-18
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-01
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-27
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify cpu to unbreak tests.Evan Cheng2012-04-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-10
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for 'msr' plain 'cpsr' operand.Jim Grosbach2012-04-05
| | | | | | | | Plain 'cpsr' is an alias for 'cpsr_fc'. rdar://11153753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-30
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-30
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-30
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM optional operand on MRC/MCR assembly instructions.Jim Grosbach2012-03-16
| | | | | | rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-18
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing of 'mov rd, rn, rrx'.Jim Grosbach2011-12-21
| | | | | | | | Maps to the RRX instruction. Missed this case earlier. rdar://10615373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach2011-12-21
| | | | | | | | These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach2011-12-14
| | | | | | | | | | When 'cmp rn #imm' doesn't match due to the immediate not being representable, but 'cmn rn, #-imm' does match, use the latter in place of the former, as it's equivalent. rdar://10552389 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-13
| | | | | | | rdar://10549767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for 146516Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM thumb2 parsing of "rsb rd, rn, #0".Jim Grosbach2011-12-13
| | | | | | | rdar://10549741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 alias for long-form pop and friends.Jim Grosbach2011-12-07
| | | | | | rdar://10542474 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2: MUL two-operand form encoding operand order fix.Jim Grosbach2011-12-06
| | | | | | | | | Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we match gas. rdar://10532439 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
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