| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | ARM: permit bare dmb/dsb/isb aliases on Cortex-M0 | Tim Northover | 2013-11-05 |
| | | | | | | | | | Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8 | ||
| * | ARM: allow cortex-m0 to use hint instructions | Tim Northover | 2013-10-07 |
| The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8 | |||
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