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* Add TB encoding to VEX versions of SSE fp logical operations to fix disassemblerCraig Topper2011-08-19
* STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST fo...Owen Anderson2011-08-18
* Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ...Owen Anderson2011-08-18
* Improve handling of failure and unpredictable cases for CPS, STR, and SMLA in...Owen Anderson2011-08-18
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-18
* More Thumb1 decoding tests.Owen Anderson2011-08-18
* Test commit; adding test for invalid LDRD which was part of the patch for r13...James Molloy2011-08-18
* Port over BL/BLX to disassembly tests.Owen Anderson2011-08-18
* Port new Thumb1 encoding tests over to decoding tests.Owen Anderson2011-08-17
* Start building a Thumb1 decoding test file based on the Thumb1 parsing/encodi...Owen Anderson2011-08-17
* Allow the MCDisassembler to return a "soft fail" status code, indicating an i...Owen Anderson2011-08-17
* Add a test file for Thumb2 NEON.Owen Anderson2011-08-15
* Add some more comprehensive VFP decoding tests.Owen Anderson2011-08-15
* Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM ...Owen Anderson2011-08-15
* Add a test for Thumb1 LDRSH decoding.Owen Anderson2011-08-15
* Add testcase for STRH. Patch by James Molloy.Owen Anderson2011-08-15
* Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.Owen Anderson2011-08-15
* Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson2011-08-15
* Fix problems decoding the to/from-lane NEON memory instructions, and add a co...Owen Anderson2011-08-15
* Fix some remaining issues with decoding ARM-mode memory instructions, and add...Owen Anderson2011-08-12
* Port over the basic ARM encodings test file to a decoding test file. Greatly...Owen Anderson2011-08-12
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-11
* Improve operand validation for Thumb2 addressing modes.Owen Anderson2011-08-11
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-11
* Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson2011-08-11
* Tighten operand decoding of addrmode2 instruction. The offset register canno...Owen Anderson2011-08-11
* Correct immediate range for shifter operands. Patch by James Molloy, with ad...Owen Anderson2011-08-11
* Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson2011-08-11
* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-10
* Push GPRnopc through a large number of instruction definitions to tighten ope...Owen Anderson2011-08-10
* Tighten operand checking of register-shifted-register operands.Owen Anderson2011-08-09
* Tighten operand checking on memory barrier instructions.Owen Anderson2011-08-09
* Tighten operand checking on CPS instructions.Owen Anderson2011-08-09
* Create a new register class for the set of all GPRs except the PC. Use it to...Owen Anderson2011-08-09
* ARM Disassembler: sign extend branch immediates.Benjamin Kramer2011-08-09
* Tighten Thumb1 branch predicate decoding.Owen Anderson2011-08-09
* Replace the existing ARM disassembler with a new one based on the FixedLenDec...Owen Anderson2011-08-09
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-03
* ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach2011-07-29
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-19
* Make the disassembler able to disassemble a bunch of instructions with names ...Eli Friedman2011-07-16
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ...Owen Anderson2011-07-15
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-11
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-22
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immedi...Johnny Chen2011-05-18
* Add tests for A8.6.110 NOP.Johnny Chen2011-04-27
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) s...Johnny Chen2011-04-22
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-15
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-15
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* inst...Johnny Chen2011-04-15
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