summaryrefslogtreecommitdiff
path: root/test/MC/X86/x86-64.s
Commit message (Collapse)AuthorAge
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-14
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-08
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test cases for the various instruction alias and Intel syntax fixes that ↵Craig Topper2013-07-26
| | | | | | have gone in lately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187188 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-23
| | | | | | normal movsl instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-22
| | | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r186813: More Intel syntax alias fixes. With the addition of ↵Craig Topper2013-07-22
| | | | | | suppressing some of the aliases from being emitted by the asm printer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-11
| | | | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, ↵Craig Topper2013-01-06
| | | | | | | | | | | | | cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix. cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix. Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix encoding of 'movd %xmm0, %rax'Jim Grosbach2012-08-31
| | | | | | | The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v' prefix, resulting in mis-assembly of the vanilla movd instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162963 91177308-0d34-0410-b5e6-96231b3b80d8
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-11
| | | | | | | ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the X86 assembler to not require a segment register on stringKevin Enderby2012-03-13
| | | | | | | | instruction's destination operand like it does for the source operand. Also fix a typo in the comment for X86AsmParser::isSrcOp(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman2012-03-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152136 91177308-0d34-0410-b5e6-96231b3b80d8
* Make aliases for shld and shrd match gas. PR12173.Eli Friedman2012-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152014 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: alias cqo to cqto.Benjamin Kramer2011-11-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145121 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-27
| | | | | | | | not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143112 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in ↵Craig Topper2011-10-07
| | | | | | 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-06
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that aKevin Enderby2011-07-06
| | | | | | | push with a small constant produces a 2-byte push. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134501 91177308-0d34-0410-b5e6-96231b3b80d8
* Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, ↵Eli Friedman2011-07-05
| | | | | | use proper aliases for the pclmullqlqdq and friends. PR10269. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134424 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for movntil/movntiq mnemonics. Reported on llvmdev.Eli Friedman2011-06-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for assembling "movq" when it's correct to do so, while continuingNick Lewycky2011-06-21
| | | | | | | | to emit "movd" across the board to continue supporting a Darwin assembler bug. This is the reincarnation of r133452. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133565 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r133452: "Emit movq for 64-bit register to XMM register moves..."Bob Wilson2011-06-21
| | | | | | | This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit movq for 64-bit register to XMM register moves, but continue to acceptNick Lewycky2011-06-20
| | | | | | | movd when assembling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the heuristic to emit the alias if the number of hard-coded registersBill Wendling2011-06-15
| | | | | | | are also greater than the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
* Heuristic: If the number of operands in the alias are more than the number ofBill Wendling2011-06-14
| | | | | | | operands in the aliasee, don't print the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
* As Dan pointed out, movzbl, movsbl, and friends are nicer than their aliasBill Wendling2011-04-14
| | | | | | | (movzx/movsx) because they give more information. Revert that part of the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-14
| | | | | | | cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,Chris Lattner2011-04-09
| | | | | | | | InstAlias doesn't allow matching immediate operands, so we have to write C++ code to do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
* Support explicit argument forms for the X86 string instructions.Joerg Sonnenberger2011-03-18
| | | | | | | For now, only the default segments are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
* Followup to r126970: add 64-bit encoding tests for str with reg operand.Eli Friedman2011-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the same (%dx) hack for in[bwl] as for out[bwl].Joerg Sonnenberger2011-02-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize loopz and loopnz as aliases for loope and loopne.Joerg Sonnenberger2011-02-22
| | | | | | | From Dimitry Andric. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-22
| | | | | | Patch by Jai Menon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
* implement PR9264: disambiguating 'bt mem, imm' as a btl.Chris Lattner2011-02-19
| | | | | | | | This is reasonable to do since all bt-mem forms do the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126047 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize monitor/mwait with explicit register argumentsJoerg Sonnenberger2011-02-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR8946, a missing reg/reg form of movdqu.Chris Lattner2011-01-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123242 91177308-0d34-0410-b5e6-96231b3b80d8
* Add another non-commutable instruction that gas accepts commuted forms for.Nick Lewycky2010-12-30
| | | | | | | Fixes PR8861. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122641 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize a previous change, fixing PR8855 - an valid large immediateChris Lattner2010-12-25
| | | | | | | rejected by the mc assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122557 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow a slash, '/', as a prefix separator for X86. rdar://8741045Kevin Enderby2010-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121320 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the data16 prefix.Rafael Espindola2010-11-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120224 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for r120017.Rafael Espindola2010-11-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120099 91177308-0d34-0410-b5e6-96231b3b80d8
* implement PR8524, apparently mainline gas accepts movq as an alias for movdChris Lattner2010-11-21
| | | | | | | when transfering between i64 gprs and mmx regs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119931 91177308-0d34-0410-b5e6-96231b3b80d8
* accept lret as an alias for lretl, fixing the reopened part of PR8592Chris Lattner2010-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
* implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.Chris Lattner2010-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
* implement aliases for div/idiv that have an explicit A register operand,Chris Lattner2010-11-06
| | | | | | | implementing rdar://8431864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
* add aliases for movs between seg registers and mem. There are multipleChris Lattner2010-11-06
| | | | | | | | | | | different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
* rework the rotate-by-1 instructions to be defined like theChris Lattner2010-11-06
| | | | | | | | | | | | | | shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-06
| | | | | | | | | listed in its asm string, for consistency with the other similar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
* correct suffix matching to search for s/l/t suffixes on Chris Lattner2010-11-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
* "mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner2010-11-01
| | | | | | | must be 8 bits. Support this memory form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-16 04:48:13 +0000