llvm - Unofficial llvm GIT mirror used in EmbToolkit

	Commit message (Collapse)	Author	Age
*	Add X86 SARX, SHRX, and SHLX instructions.	Craig Topper	2011-10-23
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add X86 RORX instruction	Craig Topper	2011-10-23
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
*	Rename PEXTR to PEXT. Add intrinsics for BMI instructions.	Craig Topper	2011-10-19
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add X86 PEXTR and PDEP instructions.	Craig Topper	2011-10-16
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add X86 BZHI instruction as well as BMI2 feature detection.	Craig Topper	2011-10-16
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵	Craig Topper	2011-10-16
\| \| \| \| \| \|	3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵	Craig Topper	2011-10-15
	because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8